Pulse-Based Clock Generation for Fast Interface Synchronization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing clock synchronization methods for high-speed data transmission interfaces like USB and SATA face challenges such as requiring an input reference clock, lengthy synchronization times, complex frequency locking circuits, and the need for external oscillators, which can lead to synchronization failures and increased production costs.
Innovation Solution
A clock generation method and system that utilizes pulse recognition techniques to quickly synchronize clocks by filtering input pulse signals, conducting width digitization calculations, and generating synchronized clocks without additional crystal or ceramic oscillators, incorporating temperature compensation and feedback adjustments to enhance stability and robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If phase lock loop or delay lock loop techniques are used for clock synchronization, then clock synchronization can be achieved, but the synchronization time is extended and the circuit complexity increases
Solution Approach 1:
The patent extracts the essential timing information from the training sequence by detecting pulse widths and periods, separating the clock synchronization function from the complex PLL/DLL circuitry. This allows obtaining clock synchronization without the lengthy data training sequence required by conventional methods.
Solution Approach 2:
The patent creates a simplified model of the clock signal by measuring pulse widths and periods from the training sequence, then reconstructing the clock timing information without needing the full complex frequency locking circuit. This copying approach achieves synchronization faster than conventional methods.
2Reliability
If phase lock loop or delay lock loop techniques are used for clock synchronization, then clock synchronization can be achieved, but the circuit complexity increases
Solution Approach 1:
The patent extracts the essential timing information from the training sequence by detecting pulse widths and periods, separating the clock synchronization function from the complex PLL/DLL circuitry. This allows obtaining clock synchronization without the lengthy data training sequence required by conventional methods.
Solution Approach 2:
The patent creates a simplified model of the clock signal by measuring pulse widths and periods from the training sequence, then reconstructing the clock timing information without needing the full complex frequency locking circuit. This copying approach achieves synchronization faster than conventional methods.
3Reliability
If external crystal or ceramic oscillator is used for clock generation, then clock pulses can be generated, but the production cost increases
Solution Approach 1:
The patent enables the system to generate its own clock signal by extracting timing information from the incoming training sequence itself. The pulse width detector and period detector use the incoming signal to create the clock, eliminating the need for external crystal or ceramic oscillators and reducing production costs.
Solution Approach 2:
The patent makes the incoming training sequence serve dual purposes: both as the data transmission carrier and as the reference for clock generation. By detecting pulse widths and periods from the same signal that carries data, the system eliminates the need for separate clock generation components.
Data Source
AI summary
The clock generation method contains the following steps. In a pulse recognition step, an input pulse signal is first filtered to remove a shorter signal. Then, a width digitization calculation is conducted on the remaining pulse signal. Based on the width digitization calculation, a signal is recorded and a period of the recorded signal is determined. The value of the period is delivered to a gain module. In a step for verifying the input value to D/A converter, two values are input to a D/A converter from the gain module, and the output from the D/A converter is delivered to an oscillator. The gain module determines a desired input value from the gain module to the D/A converter. In a pulse generation step, the gain module inputs the desired input value to the D/A converter which in turn delivers to the oscillator for the generation of a corresponding clock.