Pulse Counting Circuit With Balanced Delay-Line Oscillation

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Solution Overview

Problem

Existing random number generators and physical unclonable function (PUF) circuits face challenges in generating reliable random numbers and unique identifiers due to imbalances in rise and fall times of signal delays, leading to unpredictable stopping points and insufficient randomness.

Innovation Solution

A circuit design incorporating symmetrical and asymmetrical delay lines with NAND-type gates and multiplexers, where each branch introduces identical or different delays on rising and falling edges, allowing for controllable oscillation generation and improved randomness through balanced rise and fall times.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If asymmetrical delay elements are used to introduce different delays on rising and falling edges, then the circuit can generate oscillations, but the stopping point becomes unpredictable and randomness is insufficient

Engineering Contradiction:
Improvepredictability of stopping pointVSAvoidinsufficient randomness
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies asymmetry by introducing asymmetrical delay elements that create different delays for rising and falling edges. This controlled asymmetry generates oscillations with predictable stopping points while maintaining sufficient randomness through the inherent differences in rise and fall times of the delay elements

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent changes the delay parameters of the circuit by using delay elements with specific rise and fall times. By carefully selecting and adjusting these delay parameters, the circuit achieves both predictable stopping points and adequate randomness in the generated oscillations

Inventive Principle:
Principle #35Parameter changes

2Stability of the object's composition

If symmetrical delay lines are used to introduce identical delays on rising and falling edges, then rise and fall times are balanced, but oscillation generation becomes difficult

Engineering Contradiction:
Improvebalance of rise and fall timesVSAvoidinability to generate oscillations
Core Design Contradiction:
Stability of the object's compositionVSObject-generated harmful factors

Solution Approach 1:

The patent combines symmetrical delay lines with asymmetrical delay elements. The symmetrical delay lines provide balanced rise and fall times for stability, while the asymmetrical elements introduce the necessary delay differences to initiate and sustain oscillations

Inventive Principle:
Principle #4Asymmetry

3Object-generated harmful factors

If delay elements with different rise and fall times are used, then oscillations can be generated, but the stopping point becomes unpredictable

Engineering Contradiction:
Improveoscillation generationVSAvoidpredictability of stopping point
Core Design Contradiction:
Object-generated harmful factorsVSReliability

Solution Approach 1:

The patent carefully selects and adjusts the delay parameters of elements with different rise and fall times. By controlling these parameters within specific ranges, the circuit generates reliable oscillations with predictable stopping points while maintaining the necessary asymmetry for oscillation generation

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10659020B2Pulse counting circuit
Publication Date: 2020.05.19 STMICROELECTRONICS (ROUSSET) SAS
  • US10659020B2 patent drawing
  • US10659020B2 patent drawing
  • US10659020B2 patent drawing

AI summary

A circuit includes a random oscillation number generator (RONG) configured to generate first and second pulse signals at first and second RONG outputs. A first counter is coupled to the first RONG output and generates a first count at a first counter output. A second counter is coupled to the second RONG output and generates a second count at a second counter output. A selection circuit is coupled to the first and second counter outputs and to the first and second RONG outputs. A first pulse shaper is connected between the first RONG output and the first counter, and a second pulse shaper is connected between the second RONG output and the second counter.