Pulse Counting Circuit With Delay Compensation for Randomness Control
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Solution Overview
Problem
Existing random number generators face challenges in producing non-cloneable physical functions and ensuring sufficient randomness, particularly in applications requiring unique identifiers and cryptographic keys, due to unpredictable stopping conditions and imbalance between rise and fall times of signal delays.
Innovation Solution
A circuit design incorporating symmetrical and asymmetrical delay lines with NAND gates and flip-flops, allowing for controlled oscillation generation and counting, ensuring sufficient randomness by managing the difference between rise and fall times to determine the stopping point of the generator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If delay lines are used in random number generation circuits, then oscillation generation is enabled, but imbalance between rise and fall times reduces reliability
Solution Approach 1:
The patent applies asymmetry by introducing compensating asymmetric delay elements that deliberately add opposite asymmetry to counterbalance the inherent asymmetry of the delay lines. This allows the system to maintain reliable random number generation despite manufacturing variations in delay line symmetry.
Solution Approach 2:
The patent changes the delay parameters by making the delay lines configurable in length and adding controllable asymmetric delay elements. This allows dynamic adjustment of the delay characteristics to compensate for manufacturing variations and optimize randomness quality.
2Manufacturing precision
If symmetrical delay lines are used, then rise and fall times are balanced, but manufacturing precision requirements increase
Solution Approach 1:
The patent recognizes that achieving perfect symmetry is unnecessarily difficult and instead introduces compensating asymmetric elements. This approach relaxes manufacturing precision requirements by allowing asymmetric delay lines to be corrected through programmable compensation rather than requiring precise symmetric fabrication.
Solution Approach 2:
The system performs self-calibration by measuring the actual delay characteristics and automatically adjusting the compensating asymmetric delay elements to balance the overall delay. This eliminates the need for high-precision manual manufacturing while achieving the desired symmetry through automated self-adjustment.
3Reliability
If delay line length is increased to improve randomness, then oscillation period increases, but generation speed decreases
Solution Approach 1:
The patent makes the delay line configuration dynamic and reconfigurable, allowing the system to adjust the effective delay line length based on the desired trade-off between randomness quality and generation speed. This enables optimal performance for different operational requirements.
Solution Approach 2:
The patent segments the delay line into multiple configurable sections that can be independently activated. This allows the system to use only the necessary portion of the delay line for each operation, reducing the effective delay period while maintaining sufficient randomness quality for the application.
4Reliability
If multiple delay lines are used to improve randomness, then circuit complexity increases, but manufacturing cost increases
Solution Approach 1:
The patent makes the delay lines multi-functional by allowing them to serve both as the primary delay element and as part of the compensation mechanism. The same delay line infrastructure is used for both generating oscillations and providing the asymmetric compensation, eliminating the need for separate dedicated components.
Solution Approach 2:
The patent merges the symmetric delay line and asymmetric compensation elements into a unified delay circuit architecture. This integration reduces the overall component count and circuit complexity while maintaining the benefits of both symmetric oscillation generation and asymmetric compensation for improved randomness.
Data Source
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AI summary
The invention relates to a circuit for counting pulses supplied by a circuit having at least two terminals (251, 231) for supplying inverted pulse signals, comprising: a first counter (91) of the pulses of a first pulse signal supplying a first account; a second counter (93) of the pulses of a second pulse signal providing a second count; and an element (95) for selecting one of the accounts.