Pulse Delay ADC Architecture to Suppress Code Omission
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Solution Overview
Problem
Existing A/D converters face accuracy issues in outputting analog information as digital values due to code omission and parasitic capacitance, which degrade the precision of digitalization.
Innovation Solution
The digitalization device employs a configuration with a first pulse delay unit having (2n−(2m−1)) and a second pulse delay unit having (2n−(2m+1)) delay units connected in series, with an addition output unit that combines their outputs to generate a digital value, where n and m are natural numbers, thereby canceling code omission and increase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single pulse delay unit with 2^n delay units is used, then the device complexity is reduced, but code omission occurs degrading measurement precision
Solution Approach 1:
The pulse delay circuit is segmented into multiple independent delay units (first pulse delay unit with 2n-(2m-1) units and second pulse delay unit with 2n-(2m+1) units) that process signals separately. This segmentation allows parallel processing of analog signals through different delay paths, eliminating code omission by distributing the conversion process across multiple specialized sub-units rather than relying on a single complex circuit.
Solution Approach 2:
The outputs from multiple pulse delay units are merged through an addition output unit that combines the digital values from each delay unit. This merging process integrates the results from different delay paths (first delay unit output + second delay unit output) to produce a final high-precision digital value, combining the strengths of multiple simpler circuits to achieve superior accuracy.
2Measurement precision
If more delay units are added to improve measurement precision, then parasitic capacitance increases degrading reliability
Solution Approach 1:
By segmenting the total delay units into smaller groups (first pulse delay unit with fewer units and second pulse delay unit with fewer units), each group has reduced parasitic capacitance compared to a single large array. The segmentation distributes the total capacitance load across multiple smaller, manageable units, maintaining signal integrity while achieving the required measurement precision through parallel processing.
3Measurement precision
If the number of delay units is increased to reduce code omission, then device complexity and manufacturing difficulty increase
Solution Approach 1:
Instead of using a single pulse delay unit with the maximum number of delay units (2^n), the invention uses multiple pulse delay units with fewer delay units each (2n-(2m-1) and 2n-(2m+1)). This partial action approach achieves the same or better conversion precision by distributing the function across multiple units, reducing the complexity burden on any single unit while eliminating code omission through the combined output.
Data Source
AI summary
A digitalization device includes a first pulse delay unit, a second pulse delay unit, and an addition output unit. The first pulse delay unit includes (2n−(2m−1)) first delay units connected in series, and outputs a first signal according to the number of first delay units through which a first pulse signal passes. The second pulse delay unit includes (2n+(2m−1)) second delay units connected in series, and outputs a second signal according to the number of the second delay units through which a second pulse signal passes. Here, n and m are natural numbers, and n≥m. The addition output unit outputs, as a digital value, an addition value obtained by adding a numerical value based on the output of the first pulse delay unit and a numerical value based on the output of the second pulse delay unit.