Pulse Delay ADC Circuit for High Resolution With Lower Leakage
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Solution Overview
Problem
High-resolution analog-to-digital converters face challenges in reducing power dissipation while maintaining high resolution, particularly due to increased leakage current caused by lower threshold voltages in transistors used in leading-edge CMOS processes.
Innovation Solution
The design incorporates a pulse delay circuit with multiple delay units, each comprising logic gates with distinct threshold voltages, where the first transistor has a lower threshold voltage than the second transistor, allowing for efficient pulse signal delay and digital data generation with reduced power dissipation by optimizing transistor sizes and threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If transistors with lower threshold voltages are used in leading-edge CMOS processes to increase switching speed and achieve high-resolution conversion, then the analog-to-digital conversion resolution is improved, but the leakage current increases causing higher power dissipation
Solution Approach 1:
The pulse delay circuit is divided into multiple delay units (first delay unit, second delay unit, etc.), each with different transistor threshold voltages. The first delay unit uses transistors with lower threshold voltage for high-speed operation, while subsequent delay units use transistors with progressively higher threshold voltages. This segmentation allows the circuit to achieve high-resolution conversion through multiple delay stages while reducing total power dissipation by using higher threshold voltage transistors in later stages where lower speed is acceptable.
2Speed
If the threshold voltage of transistors is decreased to increase switching speed in the pulse delay circuit, then the delay time of each delay unit is reduced improving conversion speed, but the leakage current in transistors increases
Solution Approach 1:
Different delay units within the pulse delay circuit are assigned different local qualities in terms of transistor threshold voltage. The first delay unit employs transistors with lower threshold voltage to achieve fast switching speed for initial pulse delay. Subsequent delay units use transistors with higher threshold voltages, accepting slower switching speed in exchange for reduced leakage current. This local differentiation of transistor characteristics optimizes the balance between speed and power consumption across the entire conversion process.
Data Source
AI summary
In a semiconductor-integrated A/D converter, a pulse delay circuit is provided with a plurality of delay units. The plurality of delay units each includes at least one logic gate and operates based on a level of an input signal. The pulse delay circuit is configured to transfer a pulse signal through the plurality of delay units while the pulse signal is delayed by the plurality of delay units. A delay time of each of the plurality of delay units depends on the level of the input signal. The at least one logic gate is composed of at least one first transistor. The at least one first transistor has a first threshold voltage. A generating circuit is configured to obtain a number of the delay units through which the pulse signal has passed within a predetermined period to generate digital data based on the obtained number. The generating circuit is composed of at least one second transistor. The at least one second transistor has a second threshold voltage. The first threshold voltage of the at least one first transistor is lower than the second threshold voltage of the at least one second transistor.