Capacitor-Assisted Pulse Delay Circuit for Uniform ADC Timing
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Solution Overview
Problem
The stability of pulse delay circuits in A/D converters is compromised due to transistor-to-transistor variation in driving capacity, leading to non-uniform delay times and increased switching noise, which affects the resolution of A/D converted data.
Innovation Solution
Incorporating a capacitor between the signal line and the ground line in each delay unit of the pulse delay circuit to supply current for state inversion, reducing switching noise and ensuring uniform delay times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the transistors constituting the pulse delay circuit are made larger in size to reduce manufacturing tolerance effects, then the uniformity of delay time is improved, but the switching noise increases due to increased electric power consumption
Solution Approach 1:
The pulse delay circuit is divided into multiple delay units, each with transistors of different sizes. Specifically, delay units closer to the input end have larger transistors to compensate for accumulated errors, while those farther away have smaller transistors. This segmentation allows each unit to be optimized for its specific position in the signal path, reducing overall delay variation without requiring all transistors to be large.
Solution Approach 2:
Different delay units are assigned different transistor sizes based on their local requirements. The transistor size in each delay unit is locally optimized rather than uniformly sized throughout the circuit. This local quality approach ensures that each delay unit contributes appropriately to the overall delay uniformity while minimizing total power consumption and switching noise.
2Device complexity
If all delay units are designed with identical transistor sizes, then the circuit design is simplified, but manufacturing tolerance causes variation in delay time among delay units
Solution Approach 1:
The pulse delay circuit is divided into multiple delay units, each with transistors of different sizes. Specifically, delay units closer to the input end have larger transistors to compensate for accumulated errors, while those farther away have smaller transistors. This segmentation allows each unit to be optimized for its specific position in the signal path, reducing overall delay variation without requiring all transistors to be large.
Solution Approach 2:
Different delay units are assigned different transistor sizes based on their local requirements. The transistor size in each delay unit is locally optimized rather than uniformly sized throughout the circuit. This local quality approach ensures that each delay unit contributes appropriately to the overall delay uniformity while minimizing total power consumption and switching noise.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for A/D converters to produce data with high resolution and consistent delay signals, reducing the impact of manufacturing tolerance and noise on the pulse delay circuit performance.
Implementation Method 1
a capacitor connected between a signal line through which the voltage signal is applied to each of the delay units and the ground line; the capacitor serving as a current source to supply a current which each of the delay units consumes to invert a state thereof
Data Source
AI summary
The pulse delay circuit includes a plurality of delay units connected in series or in a ring, each of the delay units being constituted of at least one inverter gate circuit grounded to a ground line, and configured to delay a pulse signal passing therethrough by a delay time thereof depending on an input signal applied thereto, and a capacitor connected between a signal line through which the voltage signal is applied to each of the delay units and the ground line. The capacitor serves as a current source to supply a current which each of the delay units consumes to invert a state thereof.