Pulse Delay Circuit Structure for Stable Edge Timing

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Solution Overview

Problem

Existing delay circuits experience significant variations in delay time due to changes in manufacturing process, power supply voltage, and operating temperature, affecting their performance.

Innovation Solution

A delay circuit comprising a first and second delay unit, where the first unit delays a rising or falling edge of a pulse signal, and the second unit further delays the output signal, ensuring that the variation in delay time remains within a small range (e.g., 1%, 3%, or 5%) despite variations in the mentioned parameters.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional delay circuit is used, then the delay time can be adjusted, but the delay time varies significantly with manufacturing process, power supply voltage, and operating temperature

Engineering Contradiction:
Improvedelay time stabilityVSAvoiddelay time variation
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent changes the operating parameters of the delay circuit by introducing a control signal that adjusts the switching timing of transistors. By dynamically changing the gate voltage timing and duration, the circuit compensates for variations caused by manufacturing process, power supply voltage, and temperature, thereby stabilizing the delay time output

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements a feedback mechanism where the control signal is generated based on the detected timing characteristics of the input signal. The circuit monitors the actual delay performance and adjusts the control signal parameters accordingly, creating a closed-loop system that maintains stable delay time despite external parameter variations

Inventive Principle:
Principle #23Feedback

2Reliability

If the delay circuit is designed to be simple, then the device complexity is low, but the delay time variation with process and temperature is significant

Engineering Contradiction:
Improvedelay time consistencyVSAvoidcircuit structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the delay circuit into multiple functional modules: a control signal generation module, a switching module with multiple transistors, and an output module. Each module performs a specific function, allowing independent optimization and making the overall circuit more manageable despite the increased complexity required for temperature compensation

Inventive Principle:
Principle #1Segmentation

3Reliability

If a single delay unit is used, then the circuit is simple, but the delay time variation exceeds acceptable ranges

Engineering Contradiction:
Improvedelay time precisionVSAvoidnumber of delay units
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the temperature compensation function from the main delay path by introducing a separate control signal generation circuit. This control circuit independently generates timing signals that compensate for temperature effects without requiring multiple cascaded delay units, thus achieving precise delay time control with minimal additional complexity

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS11451219B2Delay circuit and delay structure
Publication Date: 2022.09.20 CHANGXIN MEMORY TECH INC
  • US11451219B2 patent drawing
  • US11451219B2 patent drawing
  • US11451219B2 patent drawing

AI summary

A delay circuit and a delay structure are provided. The circuit includes: a first delay unit configured to delay a rising edge and/or a falling edge of a pulse signal, where, an input terminal of the first delay unit receives the pulse signal, and an output terminal of the first delay unit outputs a first delay signal, and a second delay unit, configured to delay the first delay signal, where an input terminal of the second delay unit is connected to the output terminal of the first delay unit, and an output terminal of the second delay unit outputs a second delay signal.