Pulse Delay Circuit Layout for Narrow-Pulse Waveform Integrity

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Solution Overview

Problem

Conventional pulse delay circuits suffer from waveform distortion when the pulse width of the input signal is narrow, and the layout size of monostable multivibrators in integrated circuits is large, leading to inefficient design.

Innovation Solution

A pulse delay circuit with a novel configuration using a pull down element, first and second pull up elements, first and second delay units, and an inverted buffer, which allows for adjustable delay times and reduced layout size by employing N-type and P-type transistors, enabling precise control over the delayed pulse signal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional pulse delay circuit is used, then the pulse signal can be delayed for a specified time interval, but the waveform of the delayed pulse signal suffers from serious distortion when the pulse width is very narrow

Engineering Contradiction:
Improvewaveform qualityVSAvoidapplicability to narrow pulse signals
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The pulse delay circuit is divided into multiple functional modules: a first delay unit for delaying the rising edge, a second delay unit for delaying the falling edge, and separate pull-up and pull-down control circuits. This segmentation allows each module to be optimized independently, improving overall waveform quality for narrow pulses.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The circuit employs dynamic control of pull-up and pull-down elements based on the input pulse characteristics. The control signals adjust the switching timing of these elements adaptively, ensuring minimal distortion regardless of pulse width variations.

Inventive Principle:
Principle #15Dynamics

2Reliability

If a monostable multivibrator is used to eliminate waveform distortion, then the delayed pulse signal waveform is no longer suffered from distortion, but the layout size of the monostable multivibrator in the integrated circuit design is very large

Engineering Contradiction:
Improvewaveform qualityVSAvoidlayout size
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The invention extracts the essential delay function from the complex monostable multivibrator structure. By separating the delay functionality into independent delay units and using simple pull-up/pull-down control, the circuit achieves waveform distortion elimination without requiring the large layout area of a full monostable multivibrator.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Instead of using a complete monostable multivibrator, the invention creates a simplified version that copies only the necessary delay and waveform restoration functions. This reduced-complexity implementation maintains waveform quality while significantly reducing layout size.

Inventive Principle:
Principle #26Copying

3Reliability

If the pulse width of the input signal is very narrow, then the circuit should maintain minimal distortion, but conventional circuits fail to preserve waveform quality under these conditions

Engineering Contradiction:
Improvewaveform qualityVSAvoidperformance with narrow pulse widths
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The circuit adjusts its operating parameters dynamically based on input pulse characteristics. The pull-up and pull-down control circuits modify their switching timing and duration according to the pulse width, ensuring optimal waveform quality whether the input pulse is narrow or wide.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20150295567A1Pulse delay circuit
Publication Date: 2015.10.15 EMEMORY TECH INC
  • US20150295567A1 patent drawing
  • US20150295567A1 patent drawing
  • US20150295567A1 patent drawing

AI summary

A pulse delay circuit includes a pull down element, a first pull up element, a first delay unit, a second delay unit, a second pull up element, and an inverted buffer. The pull down element is connected to an input pulse signal, a node b and a first voltage. The first pull up element is connected to a node c, a second voltage and the node b. The first delay unit has a reset terminal. The first delay unit is connected to the node b and the node c. The second delay unit is connected to the node c and the node d. The second pull up element is connected to the node d, the second voltage and the node c. The inverted buffer is connected to the node c and the reset terminal. Moreover, a delayed pulse signal is outputted from the inverted buffer.