Pulse-Domain Arithmetic Units for Non-Uniform Signal Processing
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Solution Overview
Problem
Conventional signal processing methods using analog to digital converters (ADCs) are inefficient for applications where only specific regions of a signal are of interest, as they rely on uniform sampling based on the Nyquist criterion, which is not optimal for non-uniform signal distributions.
Innovation Solution
The development of pulse domain arithmetic units that operate on pulse trains generated by integrate and fire analog-to-pulse converters (IFCs), allowing for efficient addition and multiplication of analog signals by decomposing the area under the curve into rectangles of constant area, without requiring binary arithmetic or conventional ADC converters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uniform sampling based on Nyquist criterion is used, then signal representation is guaranteed, but sampling efficiency deteriorates for non-uniform signal distributions
Solution Approach 1:
The patent applies local quality by using variable sampling intervals that adapt to local signal characteristics. Instead of uniform sampling, the system dynamically adjusts sampling density based on signal activity in different regions, concentrating samples where signal variations are significant and reducing samples in平稳 regions, thereby improving efficiency while maintaining representation accuracy.
Solution Approach 2:
The invention implements dynamics by transitioning from static uniform sampling to dynamic adaptive sampling. The sampling rate and interval are continuously adjusted based on real-time signal analysis, allowing the system to respond to changing signal conditions and optimize sampling efficiency for non-uniform signal distributions while preserving critical signal information.
2Reliability
If conventional ADC converters are used, then signal conversion is achieved, but power consumption and area requirements increase
Solution Approach 1:
The patent employs simplified pulse generation circuits that replace complex conventional ADC converters. Instead of using high-power, large-area ADC hardware, the system uses low-power pulse generators that create pulse trains representing signal values, significantly reducing power consumption and device area while maintaining signal conversion functionality for the intended application scope.
Solution Approach 2:
The invention substitutes the mechanical/electrical conversion process of conventional ADCs with a pulse domain representation system. Analog signals are converted into pulse trains where signal amplitude is encoded in pulse density or timing, eliminating the need for traditional voltage-to-digital conversion hardware and reducing power and area requirements.
3Reliability
If conventional ADC converters are used, then signal conversion is achieved, but device area requirements increase
Solution Approach 1:
The patent uses compact pulse generation and manipulation circuits that occupy minimal device area compared to conventional ADC converters. The pulse domain processing architecture requires simple timing and counting logic rather than complex conversion hardware, dramatically reducing the area footprint while providing sufficient signal conversion capability for pulse-based processing applications.
Data Source
AI summary
Various examples of devices, methods and systems related to pulse based arithmetic units. In one example, a pulse domain device includes an augend area calculator to provide an augend area output for an augend pulse train; an addend area calculator to provide an addend area output for an addend pulse train; a resultant sum area (RSA) decoder to provide a RSA output using the augend and addend area outputs; and a pulse timing calculator to provide RSA output pulse timing. In another example, a pulse domain device includes a multiplicand area calculator to provide an multiplicand area output for a multiplicand pulse train; a multiplier area calculator to provide a multiplier area output for a multiplier pulse train; a resultant product area (RPA) decoder to provide a RPA output using the multiplicand and multiplier area outputs; and a pulse timing calculator to provide RPA output pulse timing.