Pulse-Based Duty Cycle Correction Without Phase Mixers
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Solution Overview
Problem
Existing duty cycle correction circuits for clock signals in semiconductor memory devices, such as DDR SDRAM, require phase mixers that consume significant power and silicon area, limiting their efficiency and design margin.
Innovation Solution
A duty cycle correction circuit comprising pulse generators, a clock dividing unit, and a pulse width control unit, which generates a clock signal with a half or one-Nth duty cycle by synchronizing pulse edges and adjusting pulse widths through a detecting and control mechanism, eliminating the need for phase mixers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a phase mixer is used to correct the duty cycle of a clock signal, then the duty cycle can be corrected to 50%, but the circuit consumes a large amount of power and requires a large silicon area
Solution Approach 1:
The patent extracts and eliminates the phase mixer component from the duty cycle correction circuit. By removing this power-consuming element and replacing it with a pulse generator-based approach, the circuit achieves duty cycle correction without the high power consumption and large silicon area requirements of traditional phase mixers
Solution Approach 2:
The patent replaces the electrical/phased-based phase mixer mechanism with a pulse generation and width control mechanism. This substitution uses simpler digital logic components (pulse generators, counters, and width controllers) instead of complex phase mixing circuitry, thereby reducing power consumption and area
2Manufacturing precision
If a phase mixer is used to correct the duty cycle of a clock signal, then the duty cycle can be corrected to 50%, but the circuit requires a large silicon area
Solution Approach 1:
The patent extracts and eliminates the phase mixer component from the duty cycle correction circuit. By removing this area-consuming element and replacing it with a pulse generator-based approach, the circuit achieves duty cycle correction without the large silicon area requirements of traditional phase mixers
Solution Approach 2:
The patent uses pulse signals as simplified copies or representations of the clock signal phases. Instead of using complex phase-mixed signals, the invention generates pulse signals that carry the necessary timing information in a more compact form, reducing the silicon area required for signal processing
3Speed
If the operational speed of the DDR SDRAM is increased, then the data processing speed is improved, but the design margin decreases due to duty error
Solution Approach 1:
The patent implements a feedback mechanism where the pulse width control unit continuously monitors the duty cycle of the generated clock signal and adjusts the pulse width accordingly. This closed-loop control ensures that the duty cycle remains accurate even at high operating speeds, maintaining design margin while enabling increased data processing speed
Solution Approach 2:
The patent performs preliminary duty cycle correction by generating the clock signal with the correct duty cycle before it is used in the memory device. The pulse generators and width controllers are configured in advance to produce accurately timed pulses, ensuring that the clock signal entering the memory logic already has the required 50% duty cycle, thereby maintaining reliability at high speeds
Data Source
AI summary
A duty cycle correction circuit comprises first and second pulse generators, a clock dividing unit, a detecting unit, and a pulse width control unit. The first pulse generator is configured to generate a first edge of a first pulse signal in synchronization with a first edge of a first clock signal, and the second pulse generator is configured to generate a first edge of a second pulse signal in synchronization with a second edge of the first pulse signal. The clock dividing unit is configured to generate a second clock signal by dividing the frequency of the first clock signal. The detecting unit is configured to generate a detecting signal according to the second clock signal and a time interval between the first edge of the first pulse signal and a second edge of the second pulse signal. In particular, pulse widths of the first and second pulse signals are the same and are adjustable according to a control signal from the pulse width control unit.