Digital Pulse Edge Control with Dynamic Delay Calibration
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Solution Overview
Problem
Traditional PWM circuits face limitations in achieving ultrahigh-precision digital pulse signals due to constraints in system clock frequency, requiring complex calibration methods that consume resources and fail to timely reflect changes in precision.
Innovation Solution
A circuit comprising a pulse edge control circuit, static calibration circuit, and dynamic calibration circuit to accurately control pulse widths by calculating and storing step size information, allowing for real-time adjustment of delay cells to maintain precision across varying conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the system clock frequency is increased to achieve higher pulse precision, then the pulse precision is improved, but the power consumption and circuit complexity increase significantly
Solution Approach 1:
The patent divides the delay control into multiple independent delay cells (DLL0-DLL7) that can be individually controlled. Each delay cell introduces a fixed delay (e.g., 150ps), and by selectively enabling specific cells, the system achieves fine-grained pulse width control without requiring a high-frequency clock. This segmentation allows precise pulse generation at lower clock frequencies, reducing power consumption while maintaining high precision.
Solution Approach 2:
Instead of improving precision by increasing clock frequency (time dimension), the patent introduces a spatial dimension through multiple parallel delay paths. The delay chain provides discrete delay steps that can be combined to achieve sub-clock-cycle precision. This dimensional shift from temporal to spatial control enables high precision without proportionally increasing power consumption.
2Measurement precision
If software calibration is used to calculate step size, then the pulse precision can be adjusted, but the system execution time increases and calibration cannot timely reflect changes
Solution Approach 1:
The patent pre-calculates and stores the relationship between delay cell combinations and corresponding pulse widths during circuit fabrication or initialization. The delay of each delay cell is measured and stored in lookup tables or configuration registers. During operation, the system directly queries these pre-computed values based on desired pulse widths, eliminating the need for real-time software calibration and immediately reflecting changes in working conditions.
Solution Approach 2:
The system includes built-in test circuits that can automatically measure the actual delay of each delay cell and self-calibrate the step size values. This self-service calibration mechanism operates independently of external software control, continuously maintaining accurate step size information without consuming system execution time or requiring external intervention.
3Measurement precision
If extra delay cells are added for hardware calibration, then the calibration precision is improved, but the circuit complexity and physical design difficulty increase
Solution Approach 1:
The patent designs the delay cells to serve dual purposes: they function as both the primary delay elements for pulse width modulation and as the calibration reference elements. The same delay cells used for normal PWM operation are utilized for step size calibration, eliminating the need for separate calibration-specific delay cells. This multi-functionality reduces circuit complexity while maintaining calibration precision.
Solution Approach 2:
The calibration functionality is merged with the operational delay chain. The step size calibration uses the existing delay cells in combination with test signal paths that are integrated into the same physical structure. By combining calibration and operational functions into a unified circuit architecture, the patent avoids increasing physical design complexity while achieving high calibration precision.
4Use of energy by stationary object
If the delay chain is used to achieve high precision without increasing clock frequency, then the power consumption is reduced, but the delay varies with voltage, temperature, and process requiring continuous calibration
Solution Approach 1:
The patent incorporates feedback mechanisms where the actual delay of each delay cell is continuously monitored and used to adjust the step size values. Test circuits generate calibration signals that pass through the delay cells, and the measured delays are fed back to update the step size lookup tables. This closed-loop feedback ensures that variations in delay due to voltage, temperature, or process changes are compensated in real-time, maintaining reliability without increasing power consumption significantly.
Data Source
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AI summary
Disclosed are a circuit and method for generating ultrahigh-precision digital pulse signals. The circuit comprises: a pulse edge control circuit used for delaying a signal on an input pin Input to some extent and accurately controlling positions of a rising edge and a falling edge of the pulse signal to accurately control the width of pulses and generate ultrahigh-precision pulses; a static calibration circuit used for calculating step size information representing the relationship between a work clock period of a system and a delay of delay cells in the pulse edge control circuit when the system is powered on to work, and storing the step size information, wherein the step size information is the number of delay cells through which the signal is propagated and passes within one system clock period; and a dynamic calibration circuit used for dynamically calculating step size information when a rising edge or a falling edge of each pulse in the input pin Input arrives. The method is implemented based on the circuit. The invention has the advantages of being simple in structure, easy to implement, high in precision, and suitable for a wide pulse frequency range.