Pulse-Etching Stress Layers for Coplanar CMOS Source and Drain Regions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor manufacturing, overfill of stress layers in trenches during CMOS device fabrication leads to uneven substrate surfaces and inconsistent stress distribution, affecting device performance, and conventional etching processes struggle to control overfill removal across CMOS devices of varying sizes on the same wafer.
Innovation Solution
A pulse-etching method using an etching machine with intermittent power output to plasma etch stress layers, ensuring all source and drain regions have a top surface coplanar with the substrate, regardless of varying trench sizes and pitches, by controlling etching cycles and standby times to maintain consistent etching rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional continuous etching process is used to remove overfill portions of stress layers, then etching can be performed continuously, but it is difficult to control etching consistency across CMOS devices with different trench sizes and pitches on the same wafer
Solution Approach 1:
The patent applies periodic action by using pulsed etching instead of continuous etching. The etching process is divided into repeated cycles of etching steps and standby steps. During etching steps, the etching reaction proceeds to remove overfill portions; during standby steps, the reaction is paused to allow for uniformity across different trench sizes. This periodic interruption ensures that stress layers in trenches of varying dimensions are etched consistently to be substantially coplanar with the substrate surface, resolving the contradiction between maintaining high productivity and achieving uniform etching precision across different device geometries.
2Quantity of substance
If stress layers are formed to fill trenches completely, then trenches are fully filled, but overfill occurs causing uneven substrate surface and inconsistent stress distribution
Solution Approach 1:
The patent applies the taking out principle by selectively removing the excess stress layer material that protrudes above the substrate surface. After stress layers are formed to completely fill trenches (ensuring full filling), a pulsed etching process is employed to extract only the overfill portions. The etching is controlled through repeated etching and standby steps, allowing precise removal of material until stress layers are substantially coplanar with the substrate surface. This approach maintains the benefit of complete trench filling while eliminating the harmful overfill that causes surface unevenness and stress distribution inconsistencies.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The pulse-etching process effectively removes overfill portions, achieving a uniform substrate surface and consistent stress distribution across CMOS devices, enhancing device performance by ensuring all stress layers are flush with the substrate surface.
Implementation Method 1
The stress layers are ion-doped and annealed on the both sides of each gate structure
Implementation Method 2
The stress layers are ion-doped and annealed on the both sides of each gate structure
Implementation Method 3
A pulse-etching method using an etching machine with intermittent power output to plasma etch stress layers
Data Source
AI summary
Methods for fabricating semiconductor devices are provided. Gate structures are formed on a top surface of a substrate to form semiconductor devices. Trenches are formed in the substrate on both sides of each gate structure of each semiconductor device. The trenches on the both sides of each gate structure are filled with stress layers, the stress layers in the substrate protruding over the top surface of the substrate. The stress layers are ion-doped and annealed on the both sides of each gate structure, and are pulse-etched to form a source region and a drain region of each gate structure. The pulse-etching is controlled such that the source regions and the drain regions of the plurality of semiconductor devices have a top surface coplanar with the top surface of the substrate.