Pulse-Filtered Clock Recovery for Smaller Loop Capacitors
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Solution Overview
Problem
High-speed clock and data recovery (CDR) devices require large loop capacitors for stability and performance, which occupy significant area in circuit boards, posing a challenge to reduce size without compromising performance.
Innovation Solution
A CDR device incorporating a pulse filter that adjusts the pulse width of phase state signals based on loop capacitor capacitance, allowing for reduced capacitor size without degrading stability or performance, featuring a simple and scalable circuit structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large loop capacitors are used to maintain stability and performance of the analog CDR device, then stability and performance are improved, but the occupied area on the circuit board increases
Solution Approach 1:
The patent changes the parameter of pulse width in the phase state signal to compensate for reduced loop capacitor capacitance. By dynamically adjusting the pulse width based on the capacitance value, the system maintains the required stability and performance while using smaller capacitors, thus resolving the contradiction between reliability and area occupation.
Solution Approach 2:
The patent applies preliminary anti-action by pre-adjusting the pulse width parameter before the system operates with reduced capacitance. This pre-compensation ensures that when smaller capacitors are used, the system stability is maintained through the预先 adjusted timing parameters, preventing performance degradation that would normally occur with reduced capacitance.
2Area of stationary object
If the size of the loop filter is reduced, then the occupied area decreases, but the stability and performance may be degraded
Solution Approach 1:
The patent compensates for the reduced loop filter size by changing the pulse width parameter in the phase detection stage. This parameter adjustment ensures that even with a smaller loop filter and reduced capacitance, the system maintains adequate stability and performance characteristics.
Data Source
AI summary
A clock and data recovery device that includes a first phase detector, a pulse filter, a charge pump, a loop filter and a voltage-controlled oscillator is introduced. The first phase detector generates a first phase state signal according to a data signal and a first output signal. The pulse filter adjusts the first phase state signal according to a capacitance of a loop capacitor to generate a filtered signal. The charge pump generates a pumping signal according to the filtered signal. The loop filter generates a control signal according to the pumping signal. The voltage-controlled oscillator generates a second output signal and adjust a frequency of the second output signal according to the control signal, wherein the first output signal is generated according to the second output signal.