Pulse-Based Flip-Flop Circuit for Lower Clock-to-Output Delay
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Solution Overview
Problem
Integrated circuits (ICs) using pulse-based flip-flops (FFs) face significant delays between clock and output signals due to the generation of pulse signals based on clock signals, which hampers high-speed operations.
Innovation Solution
The FF design incorporates specific transistor configurations and keeper circuits to create separate discharge and charge paths activated by clock and inverted clock signals, reducing the delay between the clock signal and output signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If a pulse-based flip-flop is used to achieve short setup time, then the setup time is reduced, but the delay between clock signal and output signal becomes large
Solution Approach 1:
The patent divides the flip-flop circuit into multiple independent transistor paths: a first path (third and fourth NMOS transistors) for discharging the first node to ground, and a second path (third and fourth PMOS transistors) for charging the first node to power voltage. This segmentation allows simultaneous operation of charge and discharge paths, reducing the overall clock-to-output delay while maintaining the pulse-based short setup time characteristic
Solution Approach 2:
The patent activates the charge and discharge paths in advance by using clock signal edges to turn on the third and fourth transistors before the pulse signal actually latches the data. This preliminary action prepares the node voltage in advance, reducing the effective delay from clock to output while preserving the short setup time benefit of pulse-based operation
Data Source
AI summary
A flip-flop (FF) includes a first n-channel metal oxide semiconductor (NMOS) transistor connected to a ground line, a first p-channel metal oxide semiconductor (PMOS) transistor connected to a power voltage line, a second NMOS transistor connecting a first node to the first NMOS transistor, a second PMOS transistor connecting the first node to the first PMOS transistor, a third NMOS transistor and a fourth NMOS transistor, connected to the second NMOS transistor in parallel, and forming a first discharge path for connecting the first node to the ground line, a third PMOS transistor and a fourth PMOS transistor, connected to the second PMOS transistor in parallel, and forming a first charge path for connecting the first node to the power voltage line, a keeper circuit connected to the first node to maintain a voltage level of the first node.