Pulse-Based Flip-Flop Timing for Shorter Setup and Constant DQ Delay
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Solution Overview
Problem
Master-slave flip flops in digital designs suffer from long setup times, leading to increased Data-to-Output (DQ) delays, which hinder the operating speed and power efficiency of application processors in mobile devices.
Innovation Solution
A pulse-based flip flop circuit design that includes a pulse generator circuit, a scan hold buffer, and a latch circuit, utilizing a NAND circuit with a direct and delay path to generate pulse signals, allowing for reduced setup times and constant DQ delays, even when data is prepared after the active clock edge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If master-slave flip flop structure is used, then ease of implementation and operating stability are improved, but setup time duration increases leading to longer DQ delays
Solution Approach 1:
The flip flop is divided into a master latch and a slave latch that operate independently with different clock phases. The master latch captures data during one clock phase while the slave latch holds the previous state, allowing data to be transferred without requiring long setup times. This segmentation enables the circuit to achieve both stability and reduced timing constraints.
2Ease of manufacture
If master-slave flip flop structure is used, then ease of implementation is improved, but DQ delay increases
Solution Approach 1:
The circuit uses dynamic clocking where the master and slave latches are enabled at different times through phase-shifted clock signals. This dynamic operation allows data to flow through the master latch during its active phase and then transfer to the slave latch, reducing the overall DQ delay while maintaining implementation simplicity.
3Speed
If high-speed flip flop circuits are used to increase operating speed, then operating frequency is improved, but power consumption increases
Solution Approach 1:
The flip flop circuit operates with periodic clock signals that alternately enable the master and slave latches. During each clock cycle, only one latch is actively switching while the other remains in a static holding state, reducing dynamic power consumption. This periodic operation allows high-speed operation while minimizing energy usage compared to continuously active circuits.
Data Source
AI summary
A pulse-based flip flop circuit includes a pulse generator generating a pulse signal and an inverted pulse signal, a scan hold buffer holding a scan input signal for a delay time, and a latch circuit including an intermediate node receiving either a data signal or the scan input signal responsive to a scan enable signal, the pulse signal and the inverted pulse signal. The pulse generator circuit includes a direct path providing a clock signal as a direct path input to a NAND circuit; a delay path including a number of plural stages that delay the clock signal and provide a delayed clock signal as a delay path input to the NAND circuit that performs a NAND operation on the direct path and delay path inputs to generate the inverted pulse signal; and a feedback path providing the pulse signal to a first stage among the stages of the delay path.