Pulse Generator Circuit With Delayed Clock for Stable Pulse Width
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Solution Overview
Problem
High-speed integrated circuit devices require pulse generators that can maintain stable pulse width despite process variations, which existing technologies have not effectively addressed.
Innovation Solution
A pulse generator circuit and internal clock generator circuit are designed to synchronize and delay clock signals, using PMOS and NMOS transistors, inverter circuits, and NOR/NAND gates to generate pulse signals with robust pulse width, capable of withstanding process variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional pulse generator circuits are used, then the circuit can operate at high speeds, but the pulse width becomes unstable due to process variation
Solution Approach 1:
The patent changes the control parameter from direct clock signal to internally generated clock signal with controlled delay. The internal clock generator circuit creates a delayed version of the clock signal that is used to control the pulse generation timing, thereby decoupling the pulse width from process variations affecting the main clock path.
Solution Approach 2:
The patent introduces an internal clock generator circuit as an intermediary between the external clock signal and the pulse generation logic. This intermediary circuit generates a delayed clock signal that serves as the control signal for the pulse width, isolating the pulse generation from direct process variations in the external clock path.
2Reliability
If the pulse width is made robust against process variation, then the pulse stability improves, but the circuit complexity increases
Solution Approach 1:
The patent segments the pulse generator into two distinct functional blocks: an internal clock generator circuit that produces the delayed control signal, and a pulse generation circuit that uses this signal. This segmentation allows each block to be optimized independently while working together to achieve stable pulse width.
Solution Approach 2:
The internal clock generator acts as an intermediary that provides a controlled delay function, separating the timing control from the pulse generation. This mediator approach achieves pulse width stability without requiring complex feedback or calibration circuits.
Data Source
AI summary
An integrated circuit device includes a clock delay circuit configured to receive a clock signal and a pulse signal and to produce an output signal therefrom. The clock delay circuit is configured to transition the output signal to a first state responsive to a first state of the clock signal and to transition the output signal to a second state responsive to a first state transition of the pulse signal. The integrated circuit device further includes a pulse generator circuit configured to receive the clock signal and the output signal and to produce the pulse signal therefrom. The pulse generator circuit is configured to generate the first state transition in the pulse signal responsive to a transition of the clock signal to a second state and to generate a second state transition in the pulse signal responsive to the transition of the output signal to the second state.