Pulse Generator Latch Circuit Reducing Gate Count
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Solution Overview
Problem
Conventional pulse generators for liquid crystal display (LCD) devices consume excessive energy and occupy more space due to the increasing number of gates triggered by clock signals, leading to unnecessary power consumption as the number of pulse generators increases.
Innovation Solution
A pulse generator design that uses a latch circuit responsive to an N-divided clock signal and a logic unit to generate a pulse signal, which is applied to the latch unit, reducing the number of gates required and minimizing space and power consumption by logically multiplying the input signal with the N-divided clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional pulse generators use multiple flip-flops triggered by clock signals to generate latch signals, then the latching function is achieved, but the number of gates increases leading to excessive space occupation and power consumption
Solution Approach 1:
The patent extracts and eliminates redundant flip-flops and gates from the conventional pulse generator circuit. By using a single flip-flop instead of multiple flip-flops, and removing unnecessary gating logic, the circuit achieves the same latching function with significantly reduced complexity and gate count, directly addressing the contradiction between reliability and device complexity
Solution Approach 2:
The patent merges the functions of multiple flip-flops and gates into a single streamlined circuit configuration. The clock signal and data signal are processed through a unified path using one flip-flop and minimal logic, combining multiple functions into a compact structure that reduces space occupation while maintaining the latching capability
2Adaptability or versatility
If the number of pulse generators increases to handle more source data lines, then the latching coverage is improved, but the power consumption increases due to more gates being triggered by clock signals
Solution Approach 1:
The patent removes redundant gating logic that was unnecessarily consuming power in each pulse generator. By eliminating extra gates and simplifying the logic structure, each pulse generator consumes less power, allowing more generators to be used across the display without proportionally increasing total power consumption
Solution Approach 2:
The patent uses periodic clock signals to trigger the simplified pulse generators only when needed, rather than continuous operation. This periodic triggering reduces power consumption by keeping gates in a low-power state between clock cycles, enabling scalable deployment across multiple data lines
3Stability of the object's composition
If conventional circuits use multiple flip-flops to ensure stable latching, then the latching stability is achieved, but the space occupation increases
Solution Approach 1:
The patent extracts and removes redundant flip-flops from the circuit, retaining only the essential single flip-flop needed for stable latching. This elimination of unnecessary storage elements reduces the circuit area while preserving the core latching stability function through optimized signal timing and logic
Solution Approach 2:
The single flip-flop in the patent performs multiple functions: it latches the data signal, generates the pulse output, and provides timing control. This multi-functional design replaces what would traditionally require multiple dedicated flip-flops, reducing space occupation while maintaining latching stability through the flip-flop's versatile operation
Data Source
AI summary
An exemplary embodiment of the present invention provides a pulse generator generating a control signal to control a latch unit included in a source driver for sequentially latching input data applied to a source data line of a display device, wherein the pulse generator includes a latch circuit latching an input signal in response to an N-divided clock signal and applying the latched input signal as an output signal, and a logic unit generating a pulse signal by logically multiplying the input signal by the N-divided clock signal, wherein the output signal is provided as an input signal to the latch circuit of another pulse generator, and the pulse signal is provided to the latch unit as the control signal.