Pulse-Latch Scan Chain with Blocking Gate for Race-Free Testing
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Solution Overview
Problem
The reduction of IC size is hindered by the use of scan chains, which require significant poly pitches due to the implementation of pulse latches and multiple inverters, leading to potential race conditions and increased size and cost.
Innovation Solution
A scan chain device with stages including pulse latches and blocking gates, where the pulse latch receives data during a first logical clock value and the blocking gate propagates data during a second logical clock value, utilizing clocked gates to reduce the probability of race conditions and poly pitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If pulse latches are used instead of scan registers to reduce poly pitch, then the poly pitch value decreases, but race conditions occur due to timing variances
Solution Approach 1:
A blocking gate is introduced as an intermediary component between the pulse latch and the output. This blocking gate acts as a mediator that controls data flow timing, preventing race conditions by ensuring data is only propagated when the clock signal indicates the appropriate time, thus resolving the timing variance issue while maintaining the compact pulse latch structure
2Reliability
If delay gates are added between pulse latches to address race conditions, then race condition probability decreases, but the size and cost of the scan chain increase
Solution Approach 1:
The blocking gate combines multiple functions into a single component: it acts as both a timing control element (replacing delay gates) and a data propagation gate. By merging the timing control function directly into the data path at the output of the pulse latch, the design eliminates the need for separate delay gates between latches, reducing overall scan chain size while maintaining reliability
3Reliability
If multiple inverters are used as delay elements in scan latches, then race conditions are addressed, but the number of poly pitches increases
Solution Approach 1:
The timing control function is extracted from the traditional delay gate implementation (multiple inverters) and repositioned to the output stage of the pulse latch. By taking out the delay function from between latches and placing a blocking gate at the output, the design eliminates unnecessary inverter chains while maintaining proper timing control, thus reducing poly pitch requirements
Data Source
AI summary
A system and method to perform scan testing using a pulse latch with a blocking gate is disclosed. In a particular embodiment, a scan latch includes a pulse latch operable to receive data while a pulse clock signal has a first logical clock value and a blocking gate coupled to an output of the pulse latch. The blocking gate is operable to propagate the data from the output of the pulse latch while the pulse clock signal has a second logical clock value.