Pulse-Latch Memory Bus Design for Bandwidth Expansion
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Solution Overview
Problem
Memory bus bandwidth is limited by propagation delays, requiring increased clock frequencies when additional buffers are added, and existing solutions do not efficiently manage data transmission timing variations.
Innovation Solution
A memory bus design utilizing a sequence of latches triggered by pulses generated for each edge of the clock signal, allowing simultaneous data sampling and transmission without increasing clock frequency, effectively doubling bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If additional buffers are added to the memory bus channel, then the propagation delay is reduced and bandwidth is increased, but the clock frequency must be increased which increases power consumption and system complexity
Solution Approach 1:
The patent uses periodic pulse signals to control multiple latches simultaneously, allowing data to be latched at different stages of the bus channel during the same clock cycle. This periodic pulsing mechanism enables increased bandwidth without requiring proportional increases in clock frequency, as the pulses are generated from the existing clock signal through division and conditioning circuits.
Solution Approach 2:
The memory bus channel is segmented into multiple latch stages, with each latch holding data at different positions along the channel. This segmentation allows data to be progressively moved through the channel in controlled stages rather than requiring a single high-speed transmission, thereby increasing effective bandwidth without proportionally increasing clock frequency requirements.
2Productivity
If additional buffers are added to the memory bus channel, then the propagation delay is reduced and bandwidth is increased, but the device complexity increases
Solution Approach 1:
The pulse generator and distribution network serve multiple functions: they simultaneously control all latch stages along the bus channel, provide timing synchronization, and enable bandwidth expansion. This multi-functionality reduces the need for separate control circuits for each latch, thereby increasing bandwidth while limiting the growth of system complexity.
Solution Approach 2:
The patent introduces pulse generator circuits and distribution networks as intermediary components between the clock signal and the latch stages. These intermediaries translate the clock signal into coordinated control pulses for multiple latches, simplifying the overall control architecture compared to direct individual latch control while achieving increased bandwidth.
3Speed
If the clock frequency is increased to accommodate additional buffers, then the data transmission speed is improved, but timing variations and delays become more critical and harder to manage
Solution Approach 1:
By using periodic pulse signals derived from the clock, the system maintains synchronized control over all latch stages. The regular periodic nature of these pulses provides inherent timing reference that helps manage timing variations, allowing faster data transmission while maintaining reliability through the structured periodic control mechanism.
Solution Approach 2:
The pulse generation and distribution system provides implicit feedback timing control, where the state of latches and data propagation timing influence the generation and distribution of subsequent control pulses. This feedback mechanism helps accommodate timing variations in different bus channel segments while maintaining overall synchronization, enabling higher speeds without sacrificing reliability.
Data Source
AI summary
A memory bus comprising a plurality of latches arranged sequentially between a source node and a destination node of a channel of the memory bus; and a pulse generator. The pulse generator is operable to generate a sequence of pulses, each sequential pulse to be simultaneously received by the plurality of latches. A pulse is generated for each edge of a clock signal. A first latch of the plurality of latches is operable to pass on a first data sample while a first pulse is received by the first latch of the plurality of latches. A second latch of the plurality of latches is operable to pass on a second data sample towards the first latch of the plurality of latches while the first pulse is simultaneously received by the first and second latches of the plurality of latches.