Pulse-Driven Level Shift Circuit for Stable Edge Conversion
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Solution Overview
Problem
Level shift circuits using RS flip flop circuits face challenges in achieving stable voltage level conversion while maintaining low electric current consumption and high-speed operativity, as pulse width variations with temperature and voltage conditions lead to inefficient energy use and potential malfunction.
Innovation Solution
A level shift circuit design incorporating a pulse signal generation unit, first and second level conversion units, and a flip flop circuit, where the pulse signal generation unit compares input and output signals to generate pulse signals for level conversion, ensuring stable output and minimizing overlap of set and reset signals, thus adapting to varying conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a typical level shift circuit is used to convert low voltage signal to high voltage signal, then the voltage level conversion is achieved, but the pulse width difference between rising and falling edges causes delay and makes precise control difficult
Solution Approach 1:
The patent divides the level shift function into two separate level conversion units (first and second level conversion units), each handling one edge transition independently. This segmentation allows precise control of rising and falling edges separately, eliminating the pulse width distortion caused by unified circuit design.
2Area of stationary object
If a level shift circuit using RS flip flop is used to convert low voltage to high voltage, then the circuit area is reduced, but when pulse width is too short the set/reset operation cannot be enabled and when pulse width is too long wasteful current consumption occurs
Solution Approach 1:
The patent dynamically adjusts the pulse width based on operating conditions by using two separate level conversion units that can independently optimize their response times. The circuit adapts to varying temperature and voltage conditions by comparing input and output signals and generating appropriate pulse widths, ensuring reliable set/reset operations without excessive current consumption.
3Reliability
If the pulse width outputted from the pulse signal generation circuit is increased to ensure reliable set/reset operation, then the level conversion stability is improved, but wasteful electric current consumption is caused
Solution Approach 1:
The patent applies partial action by generating minimum necessary pulse widths only when needed for reliable set/reset operations. The two separate level conversion units produce pulses with just sufficient duration to ensure proper operation, avoiding the excessive current consumption that would result from continuously maintaining long pulse widths.
4Power
If a typical level shift circuit is used for PWM controlled motor, then the voltage level conversion is achieved, but the delay difference between rising and falling times causes pulse width variation and makes precise control difficult
Solution Approach 1:
The patent segments the level shifting function into two independent units, each dedicated to handling either rising or falling edges. This allows independent optimization of each edge transition, eliminating the delay differences that would otherwise cause pulse width variation and control imprecision in PWM applications.
Data Source
AI summary
A level shift circuit includes a pulse signal generation unit generating first and second pulse signals with respect to an input signal, a first level conversion unit converting the first pulse signal at a first voltage to a third pulse signal at a second voltage, a second level conversion unit converting the second pulse signal at the first voltage to a fourth pulse signal at the second voltage, and a flip flop circuit making an output signal at the second voltage rise according to the third pulse signal, and making the output signal at the second voltage fall according to the fourth pulse signal. The pulse signal generation unit compares the input signal with the output signal of the flip flop circuit, and generates the first pulse signal when the input signal rises and the second pulse signal when the input signal falls, based on a non-matching comparison result.