Pulse-Assisted Level Shifter for Low-Voltage Transition Symmetry
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Solution Overview
Problem
Existing level shifters face challenges in operating efficiently at low voltages and maintaining reliability due to the asymmetry in transition times of voltage levels, which affects their speed and performance.
Innovation Solution
The proposed level shifter design includes an input block, a shifting block, a pulse generator, and transistors that generate pulses to directly connect nodes to ground or power nodes, improving the speed and reliability by quickly updating voltage levels stored at a latch, even at low voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional level shifter design is used, then device complexity is reduced, but operating speed deteriorates due to asymmetry in transition times
Solution Approach 1:
The patent applies asymmetry by introducing different pulse generation mechanisms for rising and falling edges. The pulse generator creates asymmetric pulse widths and timing characteristics that compensate for the inherent asymmetry in transistor transition times, allowing both rising and falling edges to achieve symmetric overall transition times despite using different circuit paths.
Solution Approach 2:
The pulse generator performs preliminary action by generating predistorted pulse signals before they reach the output stage. These pre-generated pulses are designed with asymmetric characteristics that anticipate and compensate for the asymmetric transition times of the output transistors, ensuring symmetric overall response.
2Reliability
If conventional level shifter design is used, then device complexity is reduced, but reliability deteriorates at low voltages
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting pulse width and amplitude parameters based on input voltage conditions. The pulse generator modifies its output parameters in response to low voltage conditions, ensuring reliable operation across different voltage ranges while maintaining circuit symmetry.
Solution Approach 2:
The circuit employs feedback mechanisms where the pulse generator monitors the state of the latch and adjusts its pulse output accordingly. This feedback ensures that proper timing and voltage levels are maintained even under low voltage conditions, improving reliability without requiring complex external control circuits.
3Speed
If asymmetric transition time compensation is implemented, then operating speed is improved, but device complexity increases due to additional pulse generation circuits
Solution Approach 1:
The patent merges the pulse generation functionality directly into the existing latch circuit structure. The pulse generator is integrated with the latch nodes, and the same transistors that form the latch also participate in pulse generation and transmission, eliminating the need for completely separate asymmetric compensation circuits.
Solution Approach 2:
The circuit elements serve multiple functions: the latch transistors perform both memory function and switching function, while the pulse generator simultaneously drives both rising and falling edges with different characteristics. This multi-functionality reduces the need for dedicated asymmetric compensation components.
4Speed
If direct node connection to ground is implemented, then transition speed is improved, but power consumption increases
Solution Approach 1:
The circuit uses periodic pulse generation instead of continuous direct connection. The pulse generator creates brief, periodic pulses that temporarily connect nodes to ground only when needed for transitions, rather than maintaining continuous low-impedance paths that would consume excessive power during steady states.
Data Source
AI summary
A level shifter including an input block that receives an input voltage swinging between a first ground voltage and a first power supply voltage and that connects one node of a first node and a second node to a first ground node, in response to the input voltage, a shifting block that mutually exchanges the voltage levels of third and fourth nodes in response to a current flowing through the one node, a pulse generator that generates a first pulse and a second pulse in response to the input voltage, a first transistor that directly connects the third node to the first ground node in response to the first pulse, and a second transistor that directly connects the fourth node to the first ground node in response to the second pulse.