Pulse-Assisted Level Shifter for Balanced Output Transitions
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Solution Overview
Problem
Conventional level shifters suffer from unbalanced transition speeds due to the inherent strength difference between NMOS and PMOS transistors, leading to slower transition from low to high logic levels for PMOS transistors.
Innovation Solution
A level shifting circuit comprising a pulse generator and a pull-up circuit that generates a pulse signal when both output nodes are at the low logic level, enabling either pull-up device to quickly pull up the output signal to the high logic level, thereby balancing transition speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional level shifter design using NMOS and PMOS transistors is used, then the circuit structure is simple, but the transition speed is unbalanced between low-to-high and high-to-low transitions
Solution Approach 1:
The pulse generator detects when both output nodes are at low logic level and generates a pulse signal in advance to activate the pull-up circuit, enabling the slower PMOS transistor to be pre-prepared for the upcoming low-to-high transition, thus balancing the transition speeds without fundamentally changing the conventional level shifter structure
Solution Approach 2:
A pulse generator and pull-up circuit are introduced as intermediary components between the conventional level shifter and the output, acting as a speed-balancing mechanism that compensates for the inherent PMOS slowness without requiring complete redesign of the original level shifter architecture
2Speed
If PMOS transistors are used for level shifting, then the circuit can be implemented with standard transistors, but the transition from low to high logic level is much slower compared to NMOS transistors
Solution Approach 1:
The invention changes the operational parameters of the PMOS transistor by introducing a pull-up circuit that provides additional current during low-to-high transitions, effectively increasing the switching speed of PMOS without changing the physical transistor characteristics or manufacturing process
Solution Approach 2:
The pulse generator provides periodic pulse signals that are synchronized with the input signal transitions, activating the pull-up circuit only when needed for low-to-high transitions, thereby improving PMOS speed without continuous additional power consumption or complexity
Data Source
AI summary
A level shifting circuit generates a pulse signal, when both of the logic levels of two complementary input signals of a level shifter has changed while both of the logic levels of two output signals of the level shifter present at low logic level, to pull up either one of the output signals of the level shifter to a second high logic level. Once the logic level of both output signals at the first output node and the second output node present complementary, the level shifting circuit stops pulling up the output signal.