Multi-Stage Pulse Width Modulator for Single-Step Narrow Pulses
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Solution Overview
Problem
Traditional pulse width modulators face challenges in generating pulses with very small widths, as the internal delay of their multiplexers is typically larger than a single unit step, limiting the minimum pulse width to the total delay of the multiplexer, which is longer than desired.
Innovation Solution
A pulse width modulator design featuring a multiplexer with high delay stages in parallel and a low delay stage, where the final stage has a delay smaller than a single unit step, allowing for pulses with widths as small as a single unit step by balancing delays across stages and using a phase locked loop to generate phase signals with varying delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a traditional multiplexer is used in the pulse width modulator, then the device structure is simple, but the minimum pulse width is limited to the total delay of the multiplexer which is larger than a single unit step
Solution Approach 1:
The multiplexer is divided into multiple stages: a first multiplexer stage with a first set of multiplexers, a second multiplexer stage with a second set of multiplexers, and a third multiplexer stage with a third set of multiplexers. Each stage processes a portion of the input signals and passes results to the next stage, allowing the minimum pulse width to be reduced below a single unit step while distributing the delay across balanced stages.
Solution Approach 2:
The patent introduces a time dimension by creating multiple delayed versions of input signals through different multiplexer paths. By combining signals with different delays from multiple stages, the system achieves fine-grained pulse width control that cannot be obtained with a single-stage multiplexer, effectively adding a temporal dimension to the signal processing.
2Manufacturing precision
If the multiplexer delay is reduced to achieve smaller pulse widths, then the minimum pulse width can approach a single unit step, but the delay balancing across stages becomes more difficult to achieve
Solution Approach 1:
By segmenting the multiplexer into three distinct stages with multiple multiplexers in each stage, the patent distributes the total delay across balanced sub-paths. Each stage handles a portion of the delay requirement, making it easier to balance the overall delay by adjusting individual stage delays rather than attempting to balance a single large delay path.
Solution Approach 2:
Different multiplexer stages are designed with different delay characteristics tailored to their specific functions. The first stage handles coarse delay adjustment, the second stage provides intermediate delay, and the third stage provides fine delay adjustment. This local optimization of delay properties in each stage enables precise overall delay balancing.
Data Source
AI summary
An integrated circuit includes a pulse width modulator. The pulse width modulator includes a multiplexer that receives a plurality of data delay signals. Each of the data delay signals is based on a data signal and a respective clock phase signal. The multiplexer includes a first multiplexer stage and a second multiplexer stage. The first multiplexer stage receives all of the data delay signals and has a relatively large delay. The second multiplexer stage receives to output signals from the first multiplexer stage and has a relatively small delay. The second multiplexer stage outputs a pulse width modulation signal that can have a pulse width corresponding to the offset between two adjacent clock phase signals.