Pulse Output Circuit Gate Potential Control for Transistor Stress Reduction
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Solution Overview
Problem
Conventional pulse output circuits suffer from transistor deterioration due to high amplitude clock signals, leading to variations in electrical characteristics and potential defective operations, as transistors are subjected to prolonged stress.
Innovation Solution
The pulse output circuit intermittently sets the gate potential of the transistor controlling the output pulse signal to a value higher than VSS, reducing stress on the transistor without lengthening its channel length, thereby suppressing transistor deterioration and electrical characteristic variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the channel length of the transistor is lengthened to suppress stress, then transistor deterioration is reduced, but the output pulse signal is delayed due to parasitic capacitance
Solution Approach 1:
The invention changes the gate potential parameter from a constant VSS to an intermittent high potential state. By periodically raising the gate potential above VSS, the transistor experiences reduced stress without requiring channel length modification, thus avoiding signal delay while improving durability
Solution Approach 2:
The gate potential is applied periodically rather than continuously. The potential intermittently transitions to a high state and returns to VSS, creating a periodic action that reduces cumulative stress on the transistor while maintaining functional operation and avoiding permanent delay effects
2Ease of operation
If the gate potential is held at VSS for a certain period to control the output pulse signal, then the transistor is subjected to prolonged stress, but the output pulse signal control is maintained
Solution Approach 1:
The gate potential transitions from continuous VSS holding to periodic high potential application. This periodic action maintains the ability to control output pulse signals while significantly reducing the cumulative stress period, thereby preventing transistor deterioration
Solution Approach 2:
The high potential is applied in advance to prevent stress accumulation. By intermittently raising the gate potential before stress becomes critical, the invention counteracts the deteriorative effect of prolonged VSS holding while preserving signal control functionality
Data Source
AI summary
An object is to suppress the stress applied to a transistor as well as suppressing generation of defective operation. In a pulse output circuit having a function of outputting a pulse signal and including a transistor that controls whether to set the pulse signal to high level, in a period during which the pulse signal output from the pulse output circuit is at low level, the potential of a gate of a transistor is not set to a constant value but intermittently set to a value higher than the potential VSS. Accordingly, the stress to the transistor can be suppressed.