Pulse-Pair Multi-Phase Clock Circuit for Stable Phase Spacing
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Solution Overview
Problem
Existing clock generating circuits for semiconductor devices that use phase locked loops occupy large areas, consume high power, and are susceptible to phase difference variations due to external noise, making them inefficient for generating multi-phase clocks with constant phase differences.
Innovation Solution
A clock generating circuit that uses a pulse generator to produce pulse signals with a consistent period and phase difference, and a multi-phase clock generator that enables and disables clocks based on pulse signal pairs to maintain equal phase differences between multi-phase clocks, independent of delay cell variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a phase locked loop circuit is used to generate multi-phase clocks, then multi-phase clocks can be generated, but the layout area increases and power consumption increases
Solution Approach 1:
The patent extracts the essential function of multi-phase clock generation from the complex phase locked loop circuit and implements it using a simplified pulse generator and counter-based architecture. This removes unnecessary components while retaining the core functionality of generating multiple phase-shifted clock signals.
Solution Approach 2:
The patent uses a counter to generate multiple pulse signals that are copies of the reference clock signal, each with a specific phase relationship. These copied signals are then used to control the generation of multi-phase clocks, eliminating the need for complex delay cells and phase detectors.
2Reliability
If a phase locked loop circuit is used to generate multi-phase clocks, then multi-phase clocks can be generated, but power consumption increases
Solution Approach 1:
The patent removes power-intensive components such as the charge pump, loop filter, and voltage-controlled oscillator from the traditional phase locked loop architecture. The remaining simplified circuit uses minimal power while achieving the same multi-phase clock generation function.
3Reliability
If delay cells are used to determine phase difference in a phase locked loop, then multi-phase clocks can be generated, but phase difference varies due to external noise
Solution Approach 1:
The patent uses a counter to generate multiple pulse signals that are precise copies of the reference clock, each with a predetermined phase relationship determined by the counting mechanism rather than analog delay elements. This digital copying approach eliminates sensitivity to external noise and temperature variations.
Solution Approach 2:
The patent replaces the analog delay cell mechanism with a digital counter-based system. Instead of using continuous analog delay elements that are sensitive to noise, the system uses discrete digital counting to determine phase relationships, which is inherently more stable and noise-immune.
Data Source
AI summary
A clock generating circuit, including a pulse generating unit to generate a plurality of pulse signals based on a reference clock, the pulse signals each having the same period, a phase difference between the adjacent pulse signals being a first phase difference; and a multi-phase clock generating unit to generate a plurality of multi-phase clocks, a phase difference between the adjacent multi-phase clocks being equal to a second phase difference between pulse signals of a pulse signal pair, based on a plurality of unit-phase clock generating units receiving the pulse signal pairs.