Pulse Phase Difference Circuit for Faster High-Resolution ADCs
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Solution Overview
Problem
High-speed operation of ADCs is hindered by the increased sampling time due to the need for multiple delay units connected in series, which becomes more pronounced as the bit rate increases, making it difficult to achieve high resolution and low voltage operation while maintaining conversion accuracy.
Innovation Solution
A pulse phase difference detecting circuit with a first and second delay circuit, each comprising multiple delay units with the same delay amount, connected in series, and a delay adjustment circuit to optimize the delay time, allowing for reduced sampling time and high-speed operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple delay units are connected in series to achieve high resolution, then measurement precision is improved, but sampling time increases and productivity deteriorates
Solution Approach 1:
The delay circuit is divided into multiple delay units connected in series, where each delay unit corresponds to one bit of resolution. This segmentation allows the system to achieve high-resolution measurement without requiring a single excessively long delay line, thereby reducing the total sampling time while maintaining conversion accuracy.
Solution Approach 2:
The circuit uses periodic clock signals to trigger the delay units and detect pulse positions at discrete time intervals. By synchronizing the detection process with periodic clock cycles, the system can efficiently process multiple bits in parallel across different delay units, improving sampling speed without sacrificing measurement precision.
2Measurement precision
If multiple delay units are connected in series to achieve high resolution, then measurement precision is improved, but the time required for pulse detection increases
Solution Approach 1:
The total delay time is segmented into multiple equal portions distributed across parallel delay units. Each delay unit processes a portion of the total resolution requirement, allowing simultaneous processing of multiple delay stages rather than sequential processing, thus reducing the overall sampling time while maintaining pulse position detection accuracy.
Solution Approach 2:
The circuit transitions from a single-dimensional sequential delay approach to a multi-dimensional parallel structure where multiple delay units operate simultaneously. By utilizing the time dimension for parallel processing across multiple delay stages, the system achieves high-resolution pulse detection without proportionally increasing the sampling time.
3Speed
If the power supply voltage of inverters is increased to reduce delay amount, then speed is improved, but delay variation with voltage changes increases
Solution Approach 1:
The circuit is designed to operate at optimized power supply voltage levels that balance speed and stability requirements. By carefully selecting and controlling the voltage parameters of the delay units, the system achieves sufficient operation speed while minimizing delay variation, thereby maintaining both speed and reliability.
Solution Approach 2:
The delay units are designed with dynamic characteristics that allow them to adapt to voltage variations. The circuit incorporates feedback and adjustment mechanisms that dynamically compensate for delay variations caused by voltage changes, maintaining stable operation across different voltage conditions while preserving high-speed performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables high-resolution and high-speed operation of ADCs by reducing the sampling time and stabilizing the delay variation, thereby improving conversion accuracy and facilitating efficient pulse position detection.
Implementation Method 1
utilizing the fact that a delay amount of a delay element has a voltage dependence
Data Source
AI summary
Provided is a pulse phase difference detecting circuit including: a first delay circuit that receives a first pulse signal to output a signal obtained by delaying the first pulse signal as a second pulse signal and includes multiple serially-connected delay units having the same delay amount; a second delay circuit that receives the second pulse signal and includes multiple serially-connected delay units having the delay amount; a first delay adjustment circuit that adjusts a delay amount with respect to the second pulse signal and outputs the adjusted second pulse signal back to the first delay circuit as a third pulse signal; and a pulse arrival position detecting circuit that detects a pulse arrival position of the first pulse signal based on outputs of the delay units of the first and second delay circuits that are transmitted as the third and second pulse signals, respectively.