Pulse-Repeater PLL Circuit for Wider Phase Error Detection
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Solution Overview
Problem
Conventional Phase Locked Loop (PLL) circuitry has limited gain due to circuit topology and signal frequencies, leading to deterioration in noise performance and increased sensitivity to analog non-idealities, which affects the detection of phase differences between reference and feedback signals.
Innovation Solution
The introduction of a pulse repeater circuit that generates a second pulse signal by repeating the first pulse signal, allowing for increased gain of the phase detector output signal, thereby improving noise performance and sensitivity, and enabling detection of larger phase errors before saturation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional PLL circuitry is used with standard phase detector topology, then the circuit structure is simple, but the gain is limited causing deterioration in noise performance
Solution Approach 1:
The phase detector output signal is segmented into multiple identical pulse signals through the pulse repeater circuit. Each pulse in the repeated sequence contributes to the overall gain, effectively dividing the gain requirement across multiple signal paths rather than requiring a single high-gain stage that would increase complexity.
Solution Approach 2:
The pulse repeater circuit creates multiple copies of the phase detector output signal. By generating N identical pulses for each phase detection event, the signal amplitude is effectively multiplied by N, improving the noise performance without requiring analog amplification that would add complexity.
2Measurement precision
If conventional phase detector with limited gain is used, then the device complexity is low, but the sensitivity to analog non-idealities increases
Solution Approach 1:
Multiple copies of the digital phase detector output pulse are generated by the pulse repeater circuit. This digital copying approach improves measurement precision by increasing signal amplitude without requiring complex analog circuitry, thereby reducing sensitivity to analog non-idealities such as component mismatch and thermal noise.
Solution Approach 2:
The invention replaces the need for complex analog amplification mechanisms with a digital pulse repetition approach. Instead of using high-gain analog amplifiers that are sensitive to non-idealities, the system uses digital logic to generate multiple pulse copies, achieving equivalent gain improvement with reduced sensitivity to analog imperfections.
3Adaptability or versatility
If the phase detector output signal has limited amplitude, then the circuit is simple, but the phase error range that can be detected before saturation is small
Solution Approach 1:
The pulse repeater circuit generates a periodic sequence of N identical pulses for each phase detection event. This periodic repetition of the pulse signal effectively extends the detectable phase error range by N times, allowing the PLL to accommodate larger phase deviations before saturation occurs without requiring additional circuit complexity.
Data Source
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AI summary
Phase Locked Loop, PLL, circuitry comprising a phase detector configured to generate a first pulse signal comprising at least one first pulse, a property of each first pulse being indicative of a phase difference between a reference signal and a feedback signal; a pulse repeater circuit configured, based on the first pulse signal, to generate a second pulse signal comprising, for each first pulse, a second pulse generated by repeating the corresponding first pulse; and an oscillator configured to generate the feedback signal and control a frequency of the feedback signal based on the second pulse signal.