Pulse-Driven Serializing Transmitter for Low-Power Chip Links
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Solution Overview
Problem
Conventional high-speed I/O data circuits are inadequate for efficient chip-to-chip data transfer due to excessive power consumption, inter-symbol interference, and latency issues, limiting both bandwidth and power efficiency.
Innovation Solution
A serializing transmitter with a four-stage pulse-toggled CMOS multiplexer topology and a push-pull output driver, which reduces power consumption and minimizes insertion delay, using CMOS logic and feedback control loops to manage source resistance and de-emphasis, resulting in low-power, high-speed data communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional high-speed I/O data circuits are used for chip-to-chip data transfer, then data transfer capability is provided, but power consumption is excessive and inter-symbol interference occurs
Solution Approach 1:
The patent segments the data transfer function into multiple parallel I/O circuits, each handling a portion of the data. This segmentation allows for reduced power consumption per circuit while maintaining overall high-speed capability through parallel operation, thereby resolving the contradiction between power efficiency and reliable data transfer.
Solution Approach 2:
The patent employs periodic clocking schemes and controlled switching operations in the I/O circuits to minimize unnecessary power consumption while maintaining data integrity. By activating circuits only when needed and using synchronized periodic operations, the system reduces power loss without compromising data transfer reliability.
2Productivity
If conventional I/O interfaces are used, then general purpose design flexibility is achieved, but bandwidth efficiency is limited
Solution Approach 1:
The patent changes key operational parameters of the I/O interfaces, including clock frequency, data encoding schemes, and voltage levels, to optimize bandwidth efficiency. These parameter adjustments enable higher data rates while maintaining manageable device complexity through systematic optimization rather than complete redesign.
3Ease of manufacture
If multi-chip solutions are implemented, then cost-effectiveness improves, but power supply noise increases
Solution Approach 1:
The patent introduces intermediary buffering and filtering circuits between multiple chips to isolate and reduce power supply noise. These intermediary elements act as mediators that allow cost-effective multi-chip implementations while maintaining clean power supply conditions, thereby resolving the contradiction between manufacturing economy and electrical interference.
Data Source
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AI summary
In embodiments of a serializing transmitter, the serializing transmitter includes N multiplexing drive units (200), each configured to generate a series of output pulses derived from input data signals (DA, DB) and multi-phase clock signals (CLK0-CLK6), and each multiplexing drive unit (200) including a pulse-controlled push-pull output driver (206) having first and second inputs (E, J) and an output (OUT). Each multiplexing driver unit (200) further includes a first M: 1 pulse-generating multiplexer (202) having an output (E) coupled to the first input of the pulse-controlled push-pull output driver (206), and a second M: 1 pulse-generating multiplexer (204) having an output (J) coupled to the second input of the pulse-controlled push-pull output driver (206), wherein each of the first and second M: pulse-generating multiplexers has three or fewer gate delays from a clock input to an output (E, J) of the pulse-generating multiplexer.