Pulse-Shaped Phase Detector for Distorted Error Signals
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Solution Overview
Problem
Conventional clock data recovery modules in high-speed data communications systems suffer from performance degradation due to limited circuit speeds, resulting in distorted phase error signals and excessive clock jitter, which degrades system performance.
Innovation Solution
A phase error signal equalization method is implemented using pulse shaping logic to suppress low-frequency components and maintain consistent peak amplitudes, effectively compensating for distortion caused by finite circuit speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional phase detectors are used in high-speed data communications, then the system can operate at high data rates, but the phase error signal becomes distorted due to limited circuit speeds
Solution Approach 1:
The patent changes the parameters of the phase error signal by detecting both the polarity and duration of phase errors. Instead of using a conventional binary phase detector that only detects polarity, this invention measures the temporal characteristics (duration) of phase errors to generate a refined phase error signal that is proportional to the actual phase error magnitude, thereby compensating for circuit speed limitations.
2Device complexity
If conventional binary phase detectors are used, then the circuit complexity is low, but the clock recovery accuracy degrades due to excessive clock jitter
Solution Approach 1:
The patent introduces an intermediary measurement mechanism that detects the duration of phase errors between data transitions and clock edges. This intermediary measurement (phase error duration) serves as a mediator that translates the complex relationship between clock and data signals into a refined phase error signal that accurately represents the magnitude of phase errors, thereby improving clock recovery accuracy without excessive complexity.
3Ease of operation
If the phase error signal is not equalized, then the circuit operation is simple, but the pulse areas become non-proportional causing performance degradation
Solution Approach 1:
The patent implements a feedback mechanism where the duration of phase errors is measured and used to generate a refined phase error signal with proportional pulse areas. The loop filter and voltage-controlled oscillator use this refined signal to adjust the clock frequency, creating a closed-loop feedback system that automatically compensates for phase errors and maintains reliable system performance.
Data Source
AI summary
In one embodiment, a phase error signal generated by a phase detector is equalized to compensate for the distortion in the phase error signal due to finite circuit speeds. The equalization may be based on suppressing the low frequency components of the phase error signal. For example, the amplitude of the phase error signal may be reduced when the amplitude of the phase error signal is not changing.