Pulse Shift Circuit Timing Control While Maintaining PLL Lock
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Solution Overview
Problem
Conventional pulse shift circuits require resetting both the reference pulse circuit and the pulse shift circuit to change the output timing, causing temporary unlocking of Phase Locked Loops (PLLs) and disrupting their functionality in communication devices.
Innovation Solution
A pulse shift circuit that integrates input signals, uses a quantizer to generate pulse signals, includes a delay circuit and converter to adjust signal values, and employs an input signal control circuit to manage signal flow without relying on reset signals, allowing for independent timing control of pulse signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the conventional pulse shift circuit uses reset signals to control output timing, then the output timing can be shifted by the number of clocks, but both the reference pulse circuit and pulse shift circuit must be reset, causing temporary unlocking of PLLs and disruption of device functionality
Solution Approach 1:
The invention divides the pulse shift function into two independent parts: a reference pulse circuit that generates base pulse signals, and a pulse shift circuit that processes these signals to achieve timing shift. By segmenting the functionality, the pulse shift circuit can adjust timing without requiring reset of the entire system, thus maintaining PLL lock stability while achieving precise output timing control.
Solution Approach 2:
The reference pulse circuit generates pulse signals in advance with predetermined timing characteristics. The pulse shift circuit then processes these pre-generated signals through its internal logic (including D-flip-flops and reset logic) to achieve the desired timing shift. This preliminary generation of reference pulses allows the shift circuit to operate independently without resetting the main PLL system.
2Adaptability or versatility
If the pulse shift circuit is reset to change output timing, then the timing can be adjusted, but the PLL temporarily unlocks and cannot be used until locked again
Solution Approach 1:
The invention separates the timing adjustment function into a dedicated pulse shift circuit that operates independently from the main PLL locking mechanism. This segmentation allows timing to be adjusted through the shift circuit's internal operations without affecting the PLL lock state, thereby maintaining device operational continuity while providing adaptable timing control.
Solution Approach 2:
The reference pulse circuit acts as an intermediary between the PLL system and the pulse shift circuit. It provides stable reference pulse signals that enable the shift circuit to adjust timing without directly interfering with the PLL lock mechanism. This intermediary role allows timing adaptation while preserving productivity and operational continuity.
3Measurement precision
If both reference pulse circuit and pulse shift circuit are reset simultaneously, then output timing can be controlled, but both PLLs connected to these circuits become temporarily unlocked
Solution Approach 1:
The invention implements segmentation by creating a reference pulse circuit and a pulse shift circuit as separate functional units. The reference pulse circuit generates pulses with precise timing, while the shift circuit independently processes these pulses to achieve the desired timing shift. This segmentation enables precise pulse timing control without requiring simultaneous reset of both circuits, thereby maintaining PLL lock stability.
Solution Approach 2:
The reference pulse circuit performs preliminary pulse generation with accurate timing characteristics before the signals reach the pulse shift circuit. This preliminary action establishes a stable timing foundation that allows the shift circuit to make adjustments without resetting the reference circuit or the connected PLLs, thus maintaining reliability while achieving precise timing control.
Data Source
AI summary
A problem with conventional distortion pulse shift circuits is that the output timing of a pulse signal cannot be controlled unless a reset signal is used. A pulse shift circuit according to the present invention includes: an integrator to integrate, for every clock, the first signal to be inputted; a quantizer to receive the second signal and to output a pulse signal when an integrated value of the integrator becomes equal to or larger than a signal value of the second signal; a delay circuit to delay the pulse signal; a converter disposed before or after the delay circuit to convert a signal value of the pulse signal into the signal value of the second signal; a subtractor to subtract the signal value of the pulse signal converted by the converter, from the signal value of the first signal to be inputted to the integrator; and an input signal control circuit to receive a third signal, to be disposed before the integrator, and to add a signal value corresponding to the third signal to the first signal to be inputted to the integrator or to block the first signal from being inputted to the integrator for clocks corresponding to the third signal.