Pulse Shift Circuit Timing Control Without PLL Reset
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Solution Overview
Problem
Conventional pulse shift circuits require resetting both the reference pulse circuit and the pulse shift circuit to change the output timing, causing temporary unlocking of connected PLLs, which renders them unusable until relocked.
Innovation Solution
A pulse shift circuit that integrates input signals, uses a quantizer to generate pulse signals, includes a delay circuit and converter to adjust signal values, and employs an input signal control circuit to add or block signals, allowing for timing control without resetting, thereby avoiding the need for reset signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the output timing of the pulse signal is changed by resetting both the reference pulse circuit and the pulse shift circuit, then the timing shift can be achieved, but the connected PLLs are temporarily unlocked and cannot be used until relocked
Solution Approach 1:
The pulse shift circuit performs preliminary action by pre-shifting the timing of the frequency division number control signal through a delay circuit before it reaches the divider. This allows the output timing to be adjusted without needing to reset the circuit, thereby maintaining continuous PLL lock while achieving precise timing control.
2Ease of operation
If the reset timing of the pulse shift circuit is shifted with respect to the reset timing of the reference pulse circuit, then the output timing of the pulse signal is shifted by the intended number of clocks, but both circuits must be reset to change timing
Solution Approach 1:
The invention extracts the timing shift function from the reset mechanism by introducing a separate delay circuit. Instead of using reset signals to control timing shifts, the delay circuit independently adjusts the timing of the frequency division number control signal, simplifying the control mechanism and eliminating the need for complex reset coordination.
3Reliability
If a delay circuit is used to shift the frequency division number control signal, then the output timing is shifted without resetting the PLLs, but additional circuit components are required
Solution Approach 1:
The delay circuit acts as an intermediary component between the frequency division number control signal source and the divider. It mediates the timing relationship by introducing a controlled delay, allowing the signal to be shifted in timing without affecting the PLL lock status, thus maintaining reliability while adding only a single intermediary component.
Data Source
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AI summary
A problem with conventional distortion pulse shift circuits is that the output timing of a pulse signal cannot be controlled unless a reset signal is used. A pulse shift circuit according to the present invention includes: an integrator to integrate, for every clock, the first signal to be inputted; a quantizer to receive the second signal and to output a pulse signal when an integrated value of the integrator becomes equal to or larger than a signal value of the second signal; a delay circuit to delay the pulse signal; a converter disposed before or after the delay circuit to convert a signal value of the pulse signal into the signal value of the second signal; a subtractor to subtract the signal value of the pulse signal converted by the converter, from the signal value of the first signal to be inputted to the integrator; and an input signal control circuit to receive a third signal, to be disposed before the integrator, and to add a signal value corresponding to the third signal to the first signal to be inputted to the integrator or to block the first signal from being inputted to the integrator for clocks corresponding to the third signal.