Variable Pulse Stream Edge Control for Low-Ripple DAC Output
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Solution Overview
Problem
Existing pulse width modulation (PWM) technologies face challenges in reducing ripple near zero crossings and maintaining timing resolution, leading to inefficiencies in digital-to-analog conversion and noise shaping.
Innovation Solution
The implementation of variable stream pulse width modulation (VSPWM) using splitter logic to separate input data into most significant bits (MSBs) and least significant bits (LSBs), where pulse logic generates pulses based on MSBs and edge mover logic adjusts pulse edges based on LSBs, resulting in an enhanced pulse stream with reduced ripple and improved noise shaping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional pulse width modulation is used, then the system can maintain timing resolution, but ripple near zero crossings increases and noise shaping deteriorates
Solution Approach 1:
The input digital data is segmented into two separate fields: a first field containing structure values that determine pulse patterns, and a second field containing pulse placement values that determine edge positions. This segmentation allows independent optimization of pulse generation and edge placement, enabling ripple reduction while maintaining timing resolution.
Solution Approach 2:
The patent introduces an intermediary processing stage between pulse generation and output, where edge mover logic adjusts the placement of pulse edges based on the second field values. This intermediary mechanism enables precise control over pulse positioning to reduce ripple while preserving timing information.
2Object-affected harmful factors
If conventional PWM filtering is applied to reduce ripple, then ripple decreases, but device complexity and filtering requirements increase
Solution Approach 1:
The patent performs preliminary ripple reduction by strategically placing pulse edges during the modulation stage itself, rather than relying on post-modulation filtering. The edge mover logic proactively positions pulses to minimize ripple generation, eliminating the need for complex filtering circuits and reducing overall system complexity.
3Measurement precision
If clock frequency is increased to maintain timing resolution, then timing resolution improves, but power consumption and system complexity increase
Solution Approach 1:
The patent changes the parameter representation from fixed-time-slot based to value-based pulse placement. By using the second field to directly specify pulse placement values, the system achieves fine timing resolution without requiring high clock frequencies, thereby reducing power consumption while maintaining precision.
Data Source
AI summary
An example device includes splitter logic to split an input sample having a predetermined number of bits into a first segment of most significant bits and a second segment of least significant bits. Pulse logic generates a pattern of pulses that correlate to the values of the most significant bits. Edge mover logic determines edge adjustment data based on the values of the least significant bits, the edge adjustment data representing an adjustment to at least one edge in the pattern of pulses. Combiner logic generates an enhanced pulse stream by adjusting at least one edge in the pattern of pulses based on the edge adjustment data.