Pulse-Stretcher Clock Generator Circuit for High-Speed Memory
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Solution Overview
Problem
The minimum pulse width requirements in memory devices limit the maximum system clock frequency, leading to difficulties in designing memory systems that meet the required clock frequency, resulting in potential performance delays and design roll-outs with lower performance than intended.
Innovation Solution
A memory apparatus with a single stage logic gate generates a gated memory clock with a wider pulse width than the reference clock, using a pulse stretcher circuit to overcome minimum pulse width limitations and synchronize the memory clock with the processor clock, thereby allowing higher frequency operation while meeting pulse width requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pulse latches are used in memory input paths to improve performance, then reliability of latch operation is improved, but maximum clock frequency is limited due to minimum pulse width requirements
Solution Approach 1:
The clock signal generation is segmented into multiple paths: a reference clock path and a stretched clock path. The pulse stretcher circuit segments the clock period into an active pulse portion and an extended portion, allowing different parts of the clock cycle to serve different functions - the stretched pulse ensures reliable latch operation while the extended period allows for higher frequency operation.
Solution Approach 2:
The pulse width parameter of the memory clock is changed by using a pulse stretcher circuit that generates a clock signal with a longer high-state duration than the reference clock. This parameter modification allows the memory clock to meet minimum pulse width requirements for reliable latch operation while the reference clock can operate at higher frequencies.
2Reliability
If minimum pulse width requirements are enforced to ensure proper latch operation, then reliability of memory operation is improved, but productivity of the system decreases due to performance delays
Solution Approach 1:
A pulse stretcher circuit is introduced as an intermediary between the reference clock and the memory clock. This intermediary component transforms the reference clock signal into a stretched memory clock signal that meets the minimum pulse width requirements, thereby ensuring reliable memory operation without directly limiting the reference clock frequency and maintaining system productivity.
3Productivity
If the memory clock frequency is increased to improve productivity, then system performance is improved, but the pulse width becomes too narrow to meet minimum requirements for reliable latch operation
Solution Approach 1:
The clock signal characteristics are made dynamic through the pulse stretcher circuit, which adaptively stretches the pulse width of the memory clock regardless of the reference clock frequency. This dynamic adjustment ensures that even when the reference clock operates at high frequencies for improved productivity, the resulting memory clock maintains sufficient pulse width for reliable latch operation.
Data Source
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AI summary
The apparatus provided includes a memory. The memory is configured to receive a memory clock. The apparatus also includes a single stage logic gate configured to generate the memory clock from a reference clock. The memory clock is a gated clock. Additionally, the memory clock has a wider pulse width than the reference clock. In an example, the single stage logic gate comprises a pull-up circuit configured to pull-up the memory clock, and a pull-down circuit coupled to pull-down the memory clock. In an example, the pull-up and the pull-down circuits are configured to be controlled by the reference clock, a delayed reference clock, and a gating signal. An example further includes a delay circuit configured to generate the delayed reference clock from the reference clock. An example further includes a latch configured to generate the gating signal.