Pulse Stretcher Clocking for Memory Read-Write Race Conditions
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Solution Overview
Problem
Conventional memory circuitry fails to address the race condition between input clock and data signals during read/write operations, particularly when the input clock signal does not change polarity, leading to inefficiencies in memory access.
Innovation Solution
The implementation of pulse stretcher circuitry, which includes first and second pulse stretching circuits, receives global timing pulses and provides delayed clock signals to control phase 2 latches and read-write circuitry, ensuring proper synchronization and timing margins through external pin control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory circuitry is used without pulse stretcher circuitry, then the circuit structure is simpler, but a race condition exists between input clock signal and input data signal during read/write operations
Solution Approach 1:
The pulse stretcher circuitry acts as an intermediary between the global timing pulse and the read-write circuitry. It receives the global timing pulse and generates a stretched clock signal with extended duration, mediating the timing relationship between clock and data signals to eliminate the race condition while maintaining circuit functionality.
Solution Approach 2:
The pulse stretcher circuitry performs preliminary action by pre-stretching the clock signal before it reaches the read-write circuitry. This advance timing adjustment ensures that the clock signal maintains proper polarity long enough to allow data signals to be properly captured, preventing the race condition from occurring in the first place.
2Reliability
If the input clock signal duration is extended to prevent race condition, then the timing margin is improved, but the access time and cycle time are increased
Solution Approach 1:
The pulse stretcher circuitry applies local quality by selectively stretching the clock signal only in specific timing intervals where race conditions are likely to occur. Rather than uniformly extending all clock cycles, the circuitry targets specific phases of the clock signal, maintaining proper timing margins locally without globally increasing access and cycle times.
3Reliability
If pulse stretcher circuitry is implemented to fix hold margins, then the internal and external hold margins are maintained, but the circuit complexity increases
Solution Approach 1:
The pulse stretcher circuitry merges the hold margin correction function with the existing global timing pulse distribution infrastructure. By integrating the stretching function into the clock signal distribution path already present in the memory circuitry, the design achieves hold margin correction without adding completely separate circuitry, thereby reducing overall complexity.
Data Source
AI summary
Various implementations described herein are directed to an integrated circuit having clock generation circuitry that receives an input clock signal and provides a first clock signal having a first pulse width. The integrated circuit includes first pulse-stretching circuitry coupled between the clock generation circuitry and input latch control circuitry. The first pulse-stretching circuitry receives the first clock signal and provides a second clock signal to the input latch control circuitry based on an enable signal. The second clock signal has a second pulse width that is at least greater than the first pulse width. The integrated circuit may include second pulse-stretching circuitry coupled between the clock generation circuitry and read-write circuitry. The second pulse-stretching circuitry provides a third clock signal to the read-write circuitry based on the enable signal. The third clock signal has a third pulse width that is at least greater than the first pulse width.