Pulse Synchronizer Circuit for Mixed One- and Multi-Cycle Pulses
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Solution Overview
Problem
Conventional circuitry struggles to effectively synchronize pulses across asynchronous clock domains with different speeds and pulse durations, requiring separate circuits for various applications.
Innovation Solution
A pulse synchronizer circuit comprising a one-cycle pulse synchronizer, a multi-cycle pulse synchronizer, an output multiplexer, and control logic, which converts input data signals from a source-clock domain to a destination-clock domain, handling pulses of varying durations and clock speeds by utilizing timed and untimed signal-processing elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate circuits are provided for different applications (one-cycle and multi-cycle pulse synchronizers), then reliability of pulse synchronization is improved, but device complexity increases
Solution Approach 1:
The patent combines separate one-cycle and multi-cycle pulse synchronizer circuits into a single integrated apparatus. The control logic selectively activates either the one-cycle pulse synchronizer path or the multi-cycle pulse synchronizer path based on the input pulse width, merging previously separate functions into one unified device that handles both synchronization scenarios.
Solution Approach 2:
The pulse synchronizer apparatus is designed to perform multiple functions: it can synchronize one-cycle pulses and multi-cycle pulses using the same hardware infrastructure. The control logic and multiplexers enable the circuit to adapt its behavior based on input characteristics, making the device universal rather than requiring separate dedicated circuits for each pulse type.
2Manufacturing precision
If conventional separate circuits are used for different pulse durations, then manufacturing precision for specific applications is improved, but ease of manufacture deteriorates
Solution Approach 1:
The synchronizer is segmented into distinct functional paths: a one-cycle pulse synchronizer path and a multi-cycle pulse synchronizer path. Control logic segments the operation by detecting pulse width and routing to the appropriate path. This segmentation allows each path to be optimized for its specific function while being manufactured as part of a single integrated circuit.
Solution Approach 2:
The circuit employs dynamic control based on input pulse characteristics. The control logic dynamically selects which synchronization path to activate based on whether the input pulse is one-cycle or multi-cycle duration. This dynamic adaptation is achieved through combinational logic that responds to real-time input conditions, enabling a single manufactured circuit to behave differently based on operating conditions.
Data Source
AI summary
A pulse synchronizer circuit converts an input data signal generated under a source-clock domain into an output data signal under a destination-clock domain, where the destination clock is independent of the source clock. The pulse synchronizer circuit successfully converts each data pulse in the input data signal into a corresponding data pulse in the output data signal when the source clock is faster than the destination clock, when the source clock is slower than the destination clock, when an input data pulse has a duration of one source-clock cycle, and when an input data pulse has a duration of multiple source-clock cycles. The pulse synchronizer circuit has source-domain circuitry and destination-domain circuitry. The source-domain circuitry detects input data pulses and determines whether they are single- or multi-cycle data pulses. The destination-domain circuitry generates output data pulses based on the processing of the source-domain circuitry.