Symmetric Pulse Synthesis Circuit for Equal Delay and Slew Rates
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Solution Overview
Problem
Conventional pulse synthesis circuits using wired-OR circuits face issues with asymmetric circuit structures leading to unequal delay amounts and significant delay differences between rising and falling output signal transitions due to asymmetric logical elements and differing slew rates.
Innovation Solution
A pulse synthesis circuit with symmetrically arranged drive transistors and a current mirror circuit, where the high-level periods of first pulse signals overlap with low-level periods of second pulse signals, and vice versa, to equalize delay amounts and slew rates, utilizing a current mirror circuit to synthesize outputs with equal delay and slew rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a wired-OR circuit is formed by combining multiple logical elements to synthesize pulse signals, then the circuit can generate the desired output signal, but the asymmetric circuit structure of the logical elements causes unequal delay amounts and significant delay differences between rising and falling output signal transitions
Solution Approach 1:
The patent applies asymmetry in reverse - it deliberately creates a symmetric circuit structure to counteract the inherent asymmetry of logical elements. By arranging n first drive transistors and n second drive transistors in a symmetric configuration with respect to the ground node and power supply node, the circuit achieves equal delay amounts for all pulse signals and equal slew rates for rising and falling transitions, thereby resolving the delay equality problem caused by asymmetric logical elements
2Ease of manufacture
If conventional logical elements are used in the wired-OR circuit, then the circuit implementation is straightforward, but the transition of voltage levels occurs at different slew rates causing delay difference between rising and falling output signal
Solution Approach 1:
The patent changes the electrical parameters of the circuit by introducing a current mirror circuit that forces equal current flow through symmetric paths. This parameter change ensures that the slew rates for voltage level transitions to high and low levels become equal, thereby achieving precise delay control and eliminating the delay difference between rising and falling output signal transitions
Data Source
AI summary
A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.