Pulse Train Conditioning Circuit Exponential Delay Control
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Solution Overview
Problem
Conventional trim circuits in integrated circuits require a significant number of elements to achieve dynamic and continuous delay control, leading to large area occupancy and inability to adapt to manufacturing and temperature variations, resulting in substantial pulse delay differences between integrated circuit dies and batches.
Innovation Solution
The implementation of pulse train conditioning circuits using exponential delay variation and current-based control, which reduces the number of required components and area, allowing for dynamically selectable and continuous delay adjustment by approximating exponential functions through linear input changes, utilizing switches and current sources to control capacitor discharge rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional trim circuits are used to achieve dynamic and continuous delay control, then delay adjustment capability is improved, but area occupancy increases and manufacturing precision deteriorates due to substantial pulse delay differences between dies and batches
Solution Approach 1:
The patent changes the functional parameter from linear delay adjustment to exponential delay adjustment. By using exponential delay variation, the circuit achieves a 10-bit delay range with only 5-bit control (32 units instead of 1024 units), dramatically reducing area occupancy while maintaining full delay adjustment capability
Solution Approach 2:
The patent implements dynamic delay control through current-based adjustment mechanisms. The delay can be continuously adjusted by changing current values, allowing the circuit to adapt to manufacturing variations and temperature changes while occupying minimal area
2Adaptability or versatility
If conventional trim circuits are used to achieve delay control, then delay adjustment is improved, but manufacturing precision worsens due to substantial pulse delay differences between integrated circuit dies and batches
Solution Approach 1:
The patent transitions from linear to exponential delay parameterization, which provides finer resolution at smaller delay values and coarser resolution at larger delay values. This exponential scaling compensates for manufacturing variations by providing a wider effective control range that can accommodate die-to-die and batch-to-batch variations
Solution Approach 2:
The patent incorporates trim circuits that are pre-configured with exponential delay characteristics. These circuits are designed beforehand to compensate for expected manufacturing variations, allowing the delay to be adjusted within a wide range that covers typical process variations without requiring post-manufacturing calibration
3Measurement precision
If conventional trim circuits with many elements are used, then delay control resolution is improved, but device complexity increases
Solution Approach 1:
The patent changes the control parameter from linear to exponential scaling. By using exponential delay variation, the circuit achieves 10-bit delay resolution (1024 discrete levels) with only 5-bit control signals (32 switchable units), reducing the number of elements by a factor of 32 while maintaining full resolution
Solution Approach 2:
The patent combines multiple delay units with exponential weighting into a single integrated circuit. The current-based control mechanism merges the function of what would traditionally require many separate trim elements into a unified structure that achieves the same control resolution with far fewer components
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient reduction of pulse delay differences across integrated circuit dies and batches, achieving a 10-bit delay range with 5-bit control using 32 units, compared to 1024 units in conventional circuits, while maintaining adaptability to manufacturing and temperature variations.
Implementation Method 1
a capacitor to discharge at a controlled rate to generate a delayed pulse output
Implementation Method 2
A transistor is coupled to the capacitor and a current flows through the transistor to control a discharge rate of the capacitor
Data Source
AI summary
Pulse train conditioning circuits and related methods are disclosed. An example circuit includes a first transistor having a first current terminal and a first gate terminal, a second transistor having a second current terminal and a second gate terminal, a third transistor having a third current terminal and a third gate terminal, a fourth transistor having a fourth current terminal and a fourth gate terminal, the fourth gate terminal coupled to the first through third gate terminals, a first switch having first through third terminals, the first terminal coupled to the first current terminal, the second terminal coupled to the third current terminal, and the third terminal coupled to the fourth current terminal, and a second switch having fourth through sixth terminals, the fourth terminal coupled to the second current terminal, the fifth terminal coupled to the third current terminal, and the sixth terminal coupled to the fourth current terminal.