Pulse-Train PLL Oscillator for Fine Frequency Resolution

The patent segments the frequency control into two independent parts: an integer frequency control (N) and a fractional frequency control (M/K). The integer part uses standard varactor resolution while the fractional part uses a digital counter-based approach with a divider circuit. This segmentation allows achieving fine frequency resolution (down to 1Hz) without requiring ultra-fine varactor resolution, thereby avoiding the phase noise penalty while maintaining high frequency accuracy.

The patent replaces complex analog capacitive divider structures with a digital-based frequency synthesis approach using integer and fractional numerators (N and M) combined with a divider circuit. Instead of using intricate analog capacitor networks to achieve fine frequency steps, the invention uses digital counting and division logic, significantly reducing analog complexity while achieving the same or better frequency resolution.

The patent introduces an intermediary fractional frequency control mechanism using a counter that increments M times for every K cycles of the reference frequency. This intermediary digital counting approach acts as a mediator between the integer frequency control and the final output, enabling fine frequency steps without relying on high-speed dithering or complex Sigma-Delta modulation, thereby avoiding spur degradation from varactor and timing mismatches.

The patent implements a self-calibrating frequency synthesis system where the integer and fractional frequency controls automatically align through the divider circuit logic. The system inherently ensures that N×f_ref + (M/K)×f_ref produces the correct output frequency without requiring external calibration algorithms. The divider circuit self-adjusts to maintain proper synchronization between the integer and fractional components, eliminating the need for complex calibration procedures.