Asymmetric Pulse Width Comparator for Multi-Phase Clock Skew Correction
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Solution Overview
Problem
Maintaining ideal phase differences between multi-phase clocks in integrated circuits is challenging due to noise, which affects data transfer rates and accuracy.
Innovation Solution
A clock phase correction circuit that includes variable delay circuits and pulse width comparison circuits to adjust delay values based on detected phase differences, using capacitors and comparators to generate and compare pulse signals, ensuring phase differences are maintained at 90°, 180°, and 270° between clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-phase clocks are used for data transfer, then data transfer rate increases, but phase difference accuracy deteriorates due to noise
Solution Approach 1:
The patent implements a feedback mechanism where the pulse width comparator continuously monitors the phase difference between multi-phase clocks and feeds back control signals to variable delay circuits. This closed-loop system automatically adjusts delay values to maintain accurate 90°, 180°, and 270° phase relationships despite noise interference, resolving the contradiction between high-speed data transfer and phase accuracy maintenance.
Solution Approach 2:
The patent replaces traditional mechanical or simple RC-based phase detection methods with an asymmetric pulse width comparison mechanism using capacitive integration and digital logic. This substitution provides more precise and noise-resistant phase difference measurement, enabling accurate phase maintenance at higher data transfer rates where conventional methods would fail.
2Measurement precision
If variable delay circuits are used to adjust phase, then phase difference accuracy improves, but device complexity increases
Solution Approach 1:
The patent applies partial action by implementing phase correction only where needed - using variable delay circuits selectively for specific clock phases that require adjustment, rather than complicating the entire clock distribution system. The asymmetric pulse width comparator provides sufficient precision for phase detection without requiring overly complex correction mechanisms, achieving the right balance between accuracy and complexity.
Solution Approach 2:
The patent segments the phase correction function into independent variable delay circuits for each clock phase, allowing individual adjustment without affecting other phases. This modular approach maintains phase difference accuracy while managing overall circuit complexity through functional decomposition and independent control of each clock signal path.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Accurately corrects phase skew between multi-phase clocks, enhancing data transfer reliability and precision by maintaining optimal phase relationships.
Implementation Method 1
a first capacitor set which is discharged during an activation period of a first pulse signal after being charged to a logic high level and has a first capacitance value; a second capacitor set which is discharged during an activation period of a second pulse signal after being charged to a logic high level, and has a second capacitance value
Data Source
AI summary
A clock phase correction circuit includes: a first variable delay circuit suitable for delaying a second source clock to generate a third clock; a first pulse generation circuit suitable for generating a first pulse signal that is activated from an edge of a first clock to an edge of the third clock and generating a second pulse signal that is activated from the edge of the third clock to the edge of the first clock; and a first delay value adjustment circuit suitable for detecting whether a ratio of a pulse width of the first pulse signal to a pulse width of the second pulse signal is greater or less than 1:3 to produce a detection result and adjusting a delay value of the first variable delay circuit based on the detection result.