Pulse Width Control Circuit for Stable Narrow Pulse Generation
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Solution Overview
Problem
The design of pulse signal generation circuits in semiconductor memory devices becomes increasingly challenging due to the need for precise delay adjustments as pulse widths decrease, influenced by PVT variations and the requirement for smaller clock signal pulse widths, leading to potential errors in output pulse generation.
Innovation Solution
A pulse signal generation circuit that includes a control signal generator, multiple delay units, and a pulse output unit to adjust the pulse width of the output signal based on the input pulse signal, utilizing edge detection units and shifting mechanisms to ensure stable output pulse generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If the amount of delay DY of the delay unit is increased to maintain output pulse width, then the pulse width of output pulse signal is maintained, but the design precision requirement increases due to PVT variations and decreasing input pulse width
Solution Approach 1:
The delay unit is divided into multiple delay elements (first delay element, second delay element, etc.) that can be independently controlled. This segmentation allows precise adjustment of delay amounts by selectively activating specific delay elements, thereby maintaining output pulse width without requiring excessive design precision in a single delay unit.
Solution Approach 2:
The delay amount is made dynamically adjustable through control signals that selectively activate different delay elements based on the input pulse width. This dynamic adaptation allows the circuit to maintain proper output pulse width under varying conditions (PVT variations) without requiring fixed high-precision design.
2Speed
If the pulse width of clock signal is decreased to operate at high speed, then the operating speed of semiconductor memory device is improved, but the pulse width of pulse signal becomes smaller requiring more precise delay design
Solution Approach 1:
The delay circuit dynamically adjusts its delay amount based on the actual input pulse width detected by edge detection units. When clock frequency increases and pulse width decreases, the delay unit automatically adjusts by selectively activating delay elements to maintain the required delay amount, enabling high-speed operation without compromising design precision.
Solution Approach 2:
Edge detection units detect the actual pulse width of the input clock signal and provide feedback to control the delay unit. This feedback mechanism allows the system to automatically compensate for variations in pulse width caused by high-frequency operation, maintaining accurate delay without requiring manual redesign.
3Reliability
If the amount of delay DY is precisely designed for small pulse widths, then the output pulse signal is generated correctly, but the circuit becomes more sensitive to PVT variations and design errors
Solution Approach 1:
By segmenting the delay unit into multiple controllable delay elements, the circuit achieves reliable output pulse generation without requiring a single precisely designed delay value. The segmented structure provides inherent robustness against PVT variations by allowing flexible combination of delay elements to compensate for environmental changes.
Solution Approach 2:
The circuit changes the delay parameter dynamically by selectively activating different delay elements based on detected pulse width and PVT conditions. This parameter adaptation maintains reliable operation across varying temperatures, processes, and voltages without requiring the circuit to be overly sensitive to fixed design parameters.
Data Source
AI summary
The present invention relates to a pulse signal generation circuit for changing a pulse width of an input pulse signal and outputting an output pulse signal having the changed pulse width. In an aspect, the pulse signal generation circuit may include a control signal generator configured to generate at least one control signal according to a pulse width of a input pulse signal and a pulse signal generator configured to control a pulse width of an input pulse signal in response to a control signal and to generate an output pulse signal with the controlled pulse width. The control signal controls the pulse width of the output pulse signal.