Pulse-Width DAC Architecture for Fast, Linear Conversion
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Solution Overview
Problem
Existing digital-to-analog converters (DACs) face challenges in achieving faster speed, smaller resolution, better linearity, and reduced area and power consumption while maintaining performance.
Innovation Solution
The proposed DAC architecture includes a pulse-width encoder generating a charge pulse proportional to the digital input value, a current source, a capacitor, and a charging switch, with optional negative feedback loops and multiple current sources to enhance linearity and efficiency, allowing for selective current application to the capacitor based on the charge pulse.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional DAC architectures are used to achieve faster conversion speed, then conversion speed is improved, but linearity and resolution deteriorate
Solution Approach 1:
The DAC conversion process is segmented into multiple phases: a first conversion phase using a first DAC circuit with first current sources, and a second conversion phase using a second DAC circuit with second current sources. This segmentation allows each phase to operate optimally for its specific function, achieving both high speed and high linearity without compromise.
Solution Approach 2:
The patent employs dynamic element matching (DEM) technology that dynamically switches between different current source configurations and DAC circuits during conversion. This dynamic approach adapts the circuit characteristics in real-time to maintain optimal linearity and resolution while achieving fast conversion speeds.
2Manufacturing precision
If conventional DAC architectures are used to achieve smaller resolution, then resolution is improved, but area and power consumption increase
Solution Approach 1:
The conversion process is divided into two segmented phases using different DAC circuits optimized for different resolution requirements. The first DAC handles coarse conversion with lower power consumption, while the second DAC handles fine conversion with higher precision. This segmentation achieves high overall resolution without requiring a single high-power circuit to handle all resolution levels.
Solution Approach 2:
The patent changes operational parameters between the two conversion phases, including switching between different current source configurations and adjusting switching timing. These parameter changes enable the system to achieve high resolution conversion while optimizing power consumption by using appropriate circuit configurations for each conversion stage.
3Manufacturing precision
If conventional DAC architectures are used to achieve better linearity, then linearity is improved, but conversion speed and area increase
Solution Approach 1:
The patent segments the conversion function into two specialized DAC circuits: the first DAC optimized for high-speed operation with appropriate current sources, and the second DAC optimized for high-linearity operation. By segmenting the function, each circuit can be optimized for its specific purpose without compromising the other performance metric.
Solution Approach 2:
Dynamic element matching technology is employed to dynamically switch between different current source configurations and DAC circuits during the conversion process. This dynamic switching enables the system to achieve high linearity through careful timing and configuration changes without sacrificing conversion speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves the linearity and reduces the voltage range requirements of the current source, enabling faster conversion speeds and lower power consumption while maintaining high resolution and linearity.
Implementation Method 1
a pulse-width encoder configured to generate a first charge pulse having a first pulse width proportional to the first digital input value
Implementation Method 2
a first charging switch configured to selectively apply current from the first current source to the first capacitor based on the first charge pulse
Implementation Method 3
a first capacitor configured to generate the first analog output signal
Data Source
AI summary
A digital-to-analog converter (DAC) has a pulse-width encoder that generates a charging pulse having a pulse width proportional to the DAC's digital input value. The charging pulse controls a charging switch that selectively connects a current source to a capacitor for the duration of the charging pulse. At the end of the charging pulse, a voltage corresponding to the charge stored in the capacitor forms the DAC's analog output signal. Such DACs can be configured (1) with negative-gain amplifiers across the capacitor to form a negative feedback loop, (2) with multiple parallel current sources, and/or (3) in differential architectures.