Pulse Width Measurement Circuit With Adjustable Delay Calibration
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Solution Overview
Problem
Existing pulse signal width measuring technologies in integrated circuits face accuracy issues due to complex designs, dependence on buffer time delays, and the impact of aging, leading to insufficient measurement precision and prolonged measurement times, especially when critical path time delays exceed clock cycles.
Innovation Solution
A pulse signal width measuring apparatus and method incorporating a buffer chain, path time delay adjustment circuit, and control device to reduce time delay in steps until the output of a Pth flip-flop changes, allowing for high-accuracy measurement of pulse signal width, improved by using a path time delay adjustment circuit to enhance measurement precision and reduce errors caused by aging and wiring factors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing pulse signal width measuring technologies are used, then measurement can be performed, but measurement precision is insufficient due to dependence on buffer time delays and aging effects
Solution Approach 1:
The patent replaces the mechanical/time-based buffer delay system with a digital counting system. Instead of relying on physical buffer time delays that are susceptible to aging and process variations, the invention uses a digital counter to directly count clock cycles during the pulse width measurement period, achieving higher precision and reliability that is not dependent on analog timing components.
Solution Approach 2:
The patent introduces a clock signal as an intermediary between the pulse signal and the measurement mechanism. By using a stable clock signal to gate the counting process, the system achieves precise time measurement through cycle counting rather than relying on buffer delay characteristics, thereby improving both precision and reliability against aging effects.
2Adaptability or versatility
If complex measuring designs are used, then measurement coverage can be improved, but device complexity increases
Solution Approach 1:
The patent creates a universal measurement apparatus that can measure different pulse signal widths by simply changing the counting duration or gate signal parameters, rather than requiring different hardware configurations. The same digital counting circuit can adapt to various measurement needs through software or control signal adjustments, reducing device complexity while maintaining versatility.
Solution Approach 2:
The patent achieves different measurement ranges and resolutions by changing parameters such as clock frequency, counting duration, and gate signal timing, rather than changing the physical structure of the measuring apparatus. This allows the system to adapt to different measurement requirements while maintaining a simple, fixed hardware design.
3Productivity
If traditional measurement methods are used, then measurement can be performed, but measurement time is prolonged
Solution Approach 1:
The patent replaces sequential or iterative measurement approaches with a parallel digital counting mechanism that can capture and measure pulse width in a single clock cycle period. The digital counter simultaneously counts all clock cycles during the pulse duration, achieving rapid measurement without the time-consuming sequential sampling or adjustment processes of traditional methods.
Solution Approach 2:
The patent prepares the measurement system in advance by pre-configuring the clock signal frequency and the digital counter parameters before the actual measurement begins. This preliminary setup eliminates the need for time-consuming adjustments during measurement, allowing the system to quickly capture and measure pulse widths as they occur.
Data Source
AI summary
A apparatus, method, system and medium are provided. The apparatus includes: a buffer chain, including N first buffers connected end to end, N first AND gates with one input connected to a pulse signal and the other input connected to an output of a corresponding first buffer, and N flip-flops coupled with outputs of respective first AND gates; a path time delay adjustment circuit, with an input receiving a pulse signal, and an output connected to an input terminal of the first buffer; a control apparatus, controlling the time delay produced by the adjustment circuit to be reduced by at least one step from a preset time delay during each adjustment until an output of a Pth flip-flop flips; a measuring device measuring the pulse signal's width according to an output of each flip-flop, the time delay of each first buffer and the time delay of the adjustment circuit.