Pulse-Width Statistical Circuit for Optical Disk Error Detection

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Solution Overview

Problem

The high cost of histogram apparatuses makes them unsuitable for error detection in optical disk systems, necessitating a more affordable solution for determining disk quality and analog front-end operation conditions.

Innovation Solution

A statistical circuit is integrated into the optical disk drive, comprising a measuring unit, delay units, a logical circuit, and counters to analyze pulse width signals, enabling the calculation of statistical values and average pulse widths, which can be used to adjust system parameters.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a histogram apparatus is used for error detection and quality assessment, then measurement precision is improved, but device cost increases significantly

Engineering Contradiction:
Improvequality assessment accuracyVSAvoiddevice cost
Core Design Contradiction:
Measurement precisionVSEase of manufacture

Solution Approach 1:

The patent creates a simplified copy of the histogram apparatus functionality by implementing the same pulse width measurement and statistical analysis capabilities using basic digital circuit components (counters, delay units, logic circuits) instead of expensive dedicated histogram equipment, thereby achieving comparable measurement precision at much lower cost

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent replaces expensive, complex histogram apparatus with inexpensive, easily manufacturable digital circuit components that can be integrated into the optical disk drive itself, making quality assessment affordable and accessible without requiring specialized external equipment

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

2Measurement precision

If a histogram apparatus is used for error detection, then measurement precision is improved, but device complexity increases

Engineering Contradiction:
Improvepulse width measurement accuracyVSAvoidsystem structure
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent divides the histogram apparatus functionality into separate modular components: pulse width measurement unit, delay units for time intervals, logic circuits for signal processing, and counters for statistical analysis. This segmentation allows each component to be simple and well-defined while collectively achieving precise measurement capabilities

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent replaces the complex mechanical/electronic histogram apparatus with a digital logic-based system using counters, flip-flops, and logic gates, thereby reducing physical complexity while maintaining or improving measurement precision through digital signal processing

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Measurement precision

If external histogram apparatus is used for system verification, then measurement precision is improved, but ease of operation worsens due to additional external equipment

Engineering Contradiction:
Improveerror detection accuracyVSAvoidoperation convenience
Core Design Contradiction:
Measurement precisionVSEase of operation

Solution Approach 1:

The patent merges the histogram apparatus functionality directly into the optical disk drive by integrating the pulse width measurement, delay units, logic circuits, and counters within the drive's existing control circuitry. This consolidation eliminates the need for separate external equipment, making error detection and quality assessment as convenient as normal drive operation while maintaining high measurement precision

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS7492690B2Statistical circuit
Publication Date: 2009.02.17 REALTEK SEMICON CORP
  • US7492690B2 patent drawing
  • US7492690B2 patent drawing
  • US7492690B2 patent drawing

AI summary

The statistical circuit includes a pulse-width measuring unit, serially coupling delay units, a logical circuit and counters. The pulse-width measuring unit is for receiving a sampling signal and generating a pulse-width signal. A pulse occurs on the pulse-width signal as the sampling signal has status change. The delay units include a first delay unit for receiving the pulse-width signal and outputting delay signals according to the trigger of a reference clock. The output of the first delay unit is used as a reset signal. The logic circuit is for receiving the pulse-width signal and the reset signal and generating a counting signal. The counting signal is enabled for a period of time as a pulse occurs on the pulse-width signal. The counters are respectively for receiving the delay signals and counting the number of the received delay signals in a first status as the trigger signal is enabled.