Digital Pulse Width Measurement Circuit Using Segmented Encoding

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Solution Overview

Problem

Traditional digital signal measurement circuits can only measure the integer part of digital pulse signal width due to limited precision, requiring increased sample clock frequency, which raises power consumption and hardware complexity.

Innovation Solution

A circuit and method that include a sample clock, edge detection and interrupt control unit, integer and decimal encoding units, and a signal capture chain to measure both integer and decimal parts of digital pulse signal width without increasing sample clock frequency, using a calibration control unit to dynamically adjust measurement precision.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the frequency of the sample clock is increased to improve measurement precision, then the measurement precision is improved, but the power consumption and hardware complexity greatly increase

Engineering Contradiction:
Improvemeasurement precisionVSAvoidhardware complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The measurement process is segmented into integer part measurement (using counter and sample clock) and decimal part measurement (using delay cells and capture registers). This segmentation allows high-precision measurement without requiring a high-frequency sample clock, thus avoiding increased hardware complexity and power consumption while achieving both integer and decimal parts of pulse width measurement.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If the frequency of the sample clock is increased to improve measurement precision, then the measurement precision is improved, but the power consumption greatly increases

Engineering Contradiction:
Improvemeasurement precisionVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The measurement function is segmented between a low-frequency sample clock for integer measurement and a high-resolution delay chain for decimal measurement. This allows achieving high overall measurement precision (e.g., 100 ps with 100 MHz clock) while keeping the sample clock frequency low, thereby significantly reducing power consumption compared to using a high-frequency sample clock for the entire measurement.

Inventive Principle:
Principle #1Segmentation

3Device complexity

If traditional width measurement method is used, then the hardware structure is simple, but only the integer part of pulse width can be measured

Engineering Contradiction:
Improvehardware structureVSAvoidmeasurement precision
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The delay cells are nested within the signal capture chain, with each delay cell containing a capture register. This nested structure allows the circuit to measure both integer and decimal parts of pulse width using a unified hardware architecture driven by the sample clock, achieving high measurement precision without significantly increasing hardware complexity.

Inventive Principle:
Principle #7Nested doll (Nesting)

4Measurement precision

If U.S. Pat. No. 8,384,440B2 method is used to achieve high-precision measurement, then measurement precision is improved, but independent capture delay chain and software calibration program are required

Engineering Contradiction:
Improvemeasurement precisionVSAvoidhardware and software expenditures
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The counter for integer measurement and the delay cells with capture registers for decimal measurement are merged into a unified measurement system driven by a single sample clock. The calibration function is integrated into the same hardware structure, eliminating the need for independent capture delay chains and separate software calibration programs, thus reducing both hardware and software expenditures while maintaining high measurement precision.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11852666B2Circuit and method for width measurement of digital pulse signals
Publication Date: 2023.12.26 HUNAN GREAT LEO MICROELECTRONICS CO LTD
  • US11852666B2 patent drawing
  • US11852666B2 patent drawing
  • US11852666B2 patent drawing

AI summary

Disclosed are circuit and method for width measurement of digital pulse signals. The circuit comprises: a sample clock, used to drive all registers in the circuit; an edge detection and interrupt control unit, used to detect a rising edge and a falling edge of a pulse signal on an input pin Input to control signal collection; an integer encoding unit comprising a counter and registers and used to measure an integer part μ of the width of a high or low level on the input pin Input with one period 1/f of the sample clock as a reference unit; a signal capture chain, used to sample an output level of each delay cell DLL; a decimal encoding unit, used to find out and record the propagation position of the pulse edge on the signal capture chain; and a calibration control unit, used to perform calibration.