Pulse Width Measurement Circuit Using Cycle Counting
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Solution Overview
Problem
Existing high-precision digital pulse signal width measurement circuits are complex, costly, and require significant hardware resources due to the use of delay chains and high-frequency sampling clocks.
Innovation Solution
A high-precision pulse width measurement circuit that employs a sampling clock and calibration clock circuit with a group of delay units and a clock frequency divider, along with a sampling circuit and a calibration circuit, to achieve precise measurements without a delay chain, thus reducing hardware expenditure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a delay chain is used to achieve high measurement precision, then measurement precision is improved, but hardware expenditure increases
Solution Approach 1:
The patent extracts and removes the delay chain component from the measurement system. Instead of using a delay chain to capture pulse edges, the invention uses a simple counter that counts sampling clock cycles to measure pulse width directly, eliminating the complex delay chain hardware while maintaining measurement capability
Solution Approach 2:
The patent replaces the mechanical/delay-based delay chain structure with a digital counting mechanism. The counter increments with each sampling clock cycle and captures the count value when pulse edges are detected, substituting the physical delay propagation mechanism with a digital time-counting approach
2Measurement precision
If a high-frequency sampling clock is used to achieve high measurement precision, then measurement precision is improved, but hardware expenditure and system complexity increase
Solution Approach 1:
The patent changes the approach from using high-frequency clocks to using a standard-frequency sampling clock combined with cycle counting. The measurement precision is achieved not by increasing clock frequency but by accurately counting the number of clock cycles during the pulse width, transforming the parameter from frequency to cycle count
3Measurement precision
If a delay chain is used for pulse width measurement, then measurement capability is improved, but hardware resource consumption increases
Solution Approach 1:
The patent extracts and removes the delay chain component from the measurement system. Instead of using a delay chain to capture pulse edges, the invention uses a simple counter that counts sampling clock cycles to measure pulse width directly, eliminating the complex delay chain hardware while maintaining measurement capability
Solution Approach 2:
The patent replaces the expensive and complex delay chain with a simple, low-cost counter circuit. The counter is a basic digital component that consumes minimal hardware resources compared to the multi-stage delay chain, providing the same measurement function at much lower hardware cost
Data Source
AI summary
A high-precision pulse width measurement circuit includes a sampling clock and calibration clock circuit, a sampling circuit, and a calibration circuit. The sampling clock and calibration clock circuit includes a group of delay units and a clock frequency divider, wherein each of the delay units is used for outputting a periodic sampling clock signal HRCLK, and the clock frequency divider is used for generating, according to the sampling clock signal HRCLK, a low-frequency clock signal CALCLK for sampling precision calibration. The sampling circuit, only working in an HRCLK clock domain, includes a counter HRCNT, four capture registers HRCAP1-HRCAP4, an edge detection circuit, and an interrupt control circuit. The calibration circuit includes counters CALCNT and SYSCNT, bit capture registers CALCAP and SYSCAP, a bit register CALPRD and a comparator.