Pulse Width Modulation Architecture for High-Speed Voltage Regulation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional digital PWM systems struggle to achieve high frequency and resolution for voltage regulation, particularly at frequencies above 100MHz, where the time quantization resolution is less than a single buffer of a given process node, limiting the granularity of PWM duty cycle control and output voltage adjustments.
Innovation Solution
A high-frequency digitally controlled architecture combining a delay locked loop (DLL), counter, and phase interpolators (PIs) is used to achieve high resolution for fine control of voltage regulation, enabling finer granularity of PWM duty cycle control by adjusting the on-time of bridge transistors, allowing for output voltage adjustments in steps as small as 5mV.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional digital PWM with delay line and counter is used, then area and power are optimized, but frequency resolution and time quantization precision deteriorate at high frequencies above 100MHz
Solution Approach 1:
The patent segments the delay line into multiple tap points that can be independently selected, allowing fine-grained control of pulse width at high frequencies. The delay line is divided into discrete segments corresponding to different time delays, enabling precise time quantization even at frequencies above 100MHz where traditional single-buffer approaches fail.
Solution Approach 2:
The patent introduces dynamic selection of delay line tap points based on the input digital word, allowing the system to adaptively adjust the pulse width in real-time. This dynamic approach enables high-frequency operation with fine resolution by selecting appropriate tap points rather than relying on fixed buffer delays.
2Manufacturing precision
If traditional digital PWM with counter is used, then area is reduced, but manufacturing precision and pulse width control resolution deteriorate
Solution Approach 1:
The delay line serves multiple functions: it provides both the timing reference and the pulse width control mechanism. By using the same delay line structure for both frequency reference and duty cycle control, the patent achieves high precision PWM control without requiring separate counter circuits, thereby reducing overall circuit area while maintaining manufacturing precision.
3Adaptability or versatility
If asynchronous logic is used in traditional DPWM, then flexibility is improved, but verification complexity and validation difficulty increase significantly
Solution Approach 1:
The patent employs a synchronous feedback mechanism where the delay line tap selection is controlled by a digital word that is derived from and fed back to the PWM generation logic. This feedback approach ensures monotonic and uniform PWM pulse generation without requiring complex asynchronous verification, as the system state is continuously monitored and adjusted based on the feedback signal.
4Measurement precision
If traditional PWM is used for voltage regulation, then simplicity is maintained, but output voltage adjustment granularity deteriorates
Solution Approach 1:
The patent transitions from traditional time-based PWM control to a spatial-dimension approach by using multiple tap points along the delay line. This dimensional change allows fine voltage adjustment granularity (e.g., 5mV steps) by selecting different spatial positions along the delay line, effectively adding a new degree of freedom to the control architecture without significantly increasing overall system complexity.
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
Described is a pulse width modulation architecture for high speed digitally controlled voltage regulator. Described is an apparatus which comprises: a first phase interpolator (PI) for coupling an input to a delay element of a delay line, wherein the coupling is via a selection unit; a second PI for coupling an output of the delay element of the delay line, wherein the coupling is via the selection unit; and a third PI for providing an output, the third PI calibrated according to delay settings of the first and second PIs.