Pulse Width Phase Detection With Multi-Sample Jitter Reduction
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Solution Overview
Problem
Conventional digital phase frequency detectors in ICs generate excessive jitter, which limits system performance, especially in high-speed applications like 3G-SDI systems, due to insufficient phase resolution and high cost associated with adding dither and oversampling solutions.
Innovation Solution
A pulse width determination system that uses delay chains and registers to measure pulse width differences between input signals, providing finer phase resolution and reducing jitter by accumulating and summing sampled bits to generate error values that correct phase errors, implemented in programmable logic devices like FPGAs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional digital phase frequency detector is used, then device complexity is low, but measurement precision of phase difference is insufficient leading to excessive jitter
Solution Approach 1:
The patent segments the phase detection process into multiple discrete time samples taken at different phases of the oscillator cycle. Instead of a single continuous measurement, the system divides the measurement into N discrete samples, each contributing to the final pulse width determination. This segmentation enables higher resolution phase measurement while maintaining a relatively simple digital detector architecture.
Solution Approach 2:
The patent transitions from measuring phase difference in a single time dimension to measuring across multiple time dimensions (multiple samples per oscillator cycle). By taking N samples at different phases and accumulating the results, the system effectively adds a temporal sampling dimension to the measurement process, achieving higher precision without proportionally increasing hardware complexity.
2Measurement precision
If dither and oversampling are added to compensate for jitter, then measurement precision improves, but device complexity and cost increase
Solution Approach 1:
The system uses the oscillator's own output signal to provide the sampling clock for measuring phase differences. The oscillator signal itself serves as the reference for taking multiple samples per cycle, eliminating the need for external high-speed sampling clocks or additional reference sources. This self-service approach achieves high-resolution measurement without adding external complexity.
Solution Approach 2:
The patent implements periodic sampling at multiple phases of the oscillator cycle, accumulating results over N samples per cycle. This periodic multi-phase sampling approach effectively implements oversampling and dithering functions through the natural periodicity of the oscillator, achieving jitter compensation without adding separate dither generators or oversampling hardware.
3Measurement precision
If fast sampling clock is used for high-speed oversampling, then measurement precision improves, but use of energy and device complexity increase
Solution Approach 1:
The oscillator signal provides its own clock for sampling, eliminating the need for separate high-speed sampling clock generators. By using the existing oscillator output to drive the sampling process, the system achieves high-resolution measurement without the power consumption penalty of additional high-frequency clock sources.
Solution Approach 2:
The oscillator signal serves multiple functions simultaneously: it generates the output signal being measured, provides the reference for phase comparison, and drives the sampling process. This multi-functionality eliminates the need for separate dedicated sampling clocks, reducing overall power consumption while maintaining measurement precision.
Data Source
AI summary
An embodiment of an apparatus includes a detector to receive a first input signal and a second input signal to provide a first error signal and a second error signal. A pulse width determination block receives the first and second error signals, as well as a digital oscillating signal, to output a first pulse width value and a second pulse width value, respectively. A pulse width accumulator accumulates the first and second pulse width values responsive to at least one cycle of the digital oscillating signal to provide a first accumulated value and a second accumulated value. An error generator provides an error value as a difference between the first accumulated value and the second accumulated value. The error value represents a pulse width difference between the first input signal and the second input signal indicative of a phase difference between the first input signal and the second input signal.