Pulse Width Ready Busy Logic for Memory Bus Efficiency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Non-volatile memory systems with multiple memory chips sharing a common ready/busy line suffer from inefficiencies in speed and power consumption due to constant polling and increased latency as memory operations become more autonomous and vary in timing.
Innovation Solution
Implementing a pulse width based ready/busy logic where memory chips indicate their status with pulses of varying durations, allowing the controller to detect readiness without constant polling, and using digital signals to differentiate between chips, reducing the need for serial operations and minimizing bus collisions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If constant polling is used to check die status, then the system can detect ready/busy status, but power consumption increases and latency increases
Solution Approach 1:
The patent replaces constant polling with periodic action by using interrupt-driven status notification. The die generates an interrupt signal only when its status changes (e.g., from busy to ready), allowing the controller to be notified periodically of status changes rather than continuously polling. This reduces power consumption while maintaining reliable status detection.
Solution Approach 2:
The patent implements feedback by having the die actively notify the controller of its status through interrupt signals. Instead of the controller continuously querying the die (open-loop polling), the die provides feedback about its readiness state, enabling the controller to adjust its operations based on real-time status information without constant polling overhead.
2Reliability
If constant polling is used to check die status, then the system can detect ready/busy status, but latency increases
Solution Approach 1:
The interrupt mechanism triggers status notifications only when relevant changes occur, eliminating the time wasted on periodic polling of unchanged states. The controller is immediately notified when a die transitions to ready state, reducing latency compared to waiting for the next poll cycle.
Solution Approach 2:
The die prepares and asserts the interrupt signal in advance when it transitions to a ready state, before the controller would otherwise detect the status change through polling. This preliminary notification reduces the time the controller waits to discover the die is ready.
3Device complexity
If multiple memory chips share a common ready/busy line, then bus structure is simplified, but bus collisions increase and detection becomes difficult
Solution Approach 1:
The patent segments the shared ready/busy line functionality by assigning dedicated interrupt output pins to individual memory chips. While the data bus remains shared, each chip has its own dedicated status notification path through the interrupt line, allowing the controller to distinguish which chip generated which interrupt, thereby simplifying detection without requiring complex arbitration on the data bus.
4Device complexity
If multiple memory chips share a common ready/busy line, then bus structure is simplified, but power consumption increases
Solution Approach 1:
The interrupt-driven approach activates status signaling only when necessary (periodically when status changes), rather than maintaining continuous active polling by the controller. This reduces the average power consumption of the bus system while preserving the simplified shared bus structure.
Data Source
AI summary
In a memory system where multiple memory chips communicate their ready/busy status on a shared bus line, a pulse mechanism is used for the individual memory chips to indicate their ready/busy status to the controller. In one example, the controller assigns pulse durations of differing lengths to the memory dies to allow the controller to distinguish between them. Techniques for dealing with bus collisions between the pulses of different chips are also described.