Pulse Width Control Circuit for Stable Narrow-Pulse Output

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Solution Overview

Problem

The design of pulse signal generation circuits in semiconductor memory devices becomes increasingly challenging due to the need for precise control of delay units as pulse widths decrease, especially under variations in process, voltage, and temperature, leading to instability in output pulse signals.

Innovation Solution

A pulse signal generation circuit that includes a control signal generator to adjust the pulse width of the output signal based on the input pulse signal, utilizing multiple delay units and edge detection units to control the pulse width, ensuring stable output even with small pulse widths.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Duration of action of moving object

If the amount of delay of the delay unit is increased to extend the pulse width, then the pulse width of the output signal is improved, but the design precision requirement increases and the circuit becomes unstable under PVT variations

Engineering Contradiction:
Improvepulse widthVSAvoiddelay amount precision
Core Design Contradiction:
Duration of action of moving objectVSManufacturing precision

Solution Approach 1:

The delay unit is divided into multiple sub-delay units (first delay unit, second delay unit, third delay unit) that can be independently controlled. Each sub-delay unit contributes a portion of the total delay, allowing precise control of the overall delay amount while reducing the impact of PVT variations on any single unit. This segmentation enables the circuit to achieve the required pulse width extension without demanding excessive precision from individual delay elements.

Inventive Principle:
Principle #1Segmentation

2Productivity

If the pulse width of the clock signal is reduced to increase operating speed, then the productivity is improved, but the pulse width of the generated pulse signal becomes too small, causing reliability issues

Engineering Contradiction:
Improveoperating speedVSAvoidpulse signal stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The delay unit is configured to apply delay to the input pulse signal in advance, extending the pulse width before the signal is used by other circuits. By performing this pulse width extension proactively within the pulse signal generation circuit, the circuit ensures that downstream circuits receive adequately wide pulses even when the system operates at high speeds with narrow clock periods. This preliminary action prevents reliability issues that would otherwise arise from excessively narrow pulse widths.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If the amount of delay is made very precise to maintain single-pulse output, then the measurement precision is improved, but the device complexity increases due to the need for precise inverter chain design

Engineering Contradiction:
Improvedelay amount controlVSAvoidinverter chain design
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The delay amount is made adjustable through control signals that can dynamically configure the delay unit's behavior. The delay unit responds to control signals (such as SEL signals) to adjust its delay characteristics, allowing the circuit to adapt to different operating conditions without requiring a fixed, overly complex inverter chain design. This dynamic control simplifies the overall device complexity while maintaining the ability to achieve precise delay amounts when needed.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8975932B2Pulse signal generation circuit and operating method thereof
Publication Date: 2015.03.10 SK HYNIX INC
  • US8975932B2 patent drawing
  • US8975932B2 patent drawing
  • US8975932B2 patent drawing

AI summary

The present invention relates to a pulse signal generation circuit for changing a pulse width of an input pulse signal and outputting an output pulse signal having the changed pulse width. In an aspect, the pulse signal generation circuit may include a control signal generator configured to generate at least one control signal according to a pulse width of a input pulse signal and a pulse signal generator configured to control a pulse width of an input pulse signal in response to a control signal and to generate an output pulse signal with the controlled pulse width. The control signal controls the pulse width of the output pulse signal.