Pulse Width Widener Circuit for Reliable High-Speed Data Recovery

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Solution Overview

Problem

As the frequency of clock signals increases, signal characteristics of data signals deteriorate, leading to errors in data recovery due to the shrinking 'eye' in the eye diagram, which affects the pulse width and accuracy of signal transmission.

Innovation Solution

A pulse width widener circuit comprising a delay circuit, processing circuit, and latch circuit that extends the pulse width of input signals by delaying and modifying them based on the delay time, ensuring the pulse width is either equal to or greater than the delay time, thereby improving signal recovery accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the frequency of the clock signal is increased to improve data transmission speed, then the productivity is improved, but the signal characteristics deteriorate and the eye diagram shrinks causing errors in data recovery

Engineering Contradiction:
Improvedata transmission speedVSAvoidsignal recovery accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The pulse width widener performs preliminary action by extending the pulse width of the recovered signal before it is used for further data processing. The delay circuit delays the input signal by a predetermined time, and the processing circuit generates an extended pulse signal that maintains the signal's temporal characteristics, ensuring reliable data recovery even at high clock frequencies where the eye diagram would otherwise shrink.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the pulse width is extended to improve signal recovery accuracy, then the reliability is improved, but the device complexity increases due to additional delay and processing circuits

Engineering Contradiction:
Improvesignal recovery accuracyVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The pulse width widener is segmented into distinct functional modules: a delay circuit that delays the input signal by a predetermined time, and a processing circuit that generates the extended pulse signal. This segmentation allows each module to perform its specific function independently, making the overall complex task of pulse width extension manageable and implementable with standard circuit components.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The delay circuit acts as an intermediary between the input signal and the processing circuit. It introduces a predetermined time delay that creates the temporal offset necessary for the processing circuit to generate the extended pulse signal, serving as a mediating element that enables the pulse width extension function.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Manufacturing precision

If the delay time is increased to extend the pulse width further, then the manufacturing precision of pulse width control is improved, but the loss of time in signal processing increases

Engineering Contradiction:
Improvepulse width control precisionVSAvoidsignal processing time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The delay time is set to a predetermined value that is carefully selected to provide the necessary pulse width extension for accurate signal recovery without introducing excessive delay. This parameter optimization balances the need for precise pulse width control with the constraint of minimizing signal processing time, ensuring that the extended pulse is sufficient for reliable data recovery at the target clock frequency.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9692400B2Pulse width widener and a memory system including the same
Publication Date: 2017.06.27 SAMSUNG ELECTRONICS CO LTD
  • US9692400B2 patent drawing
  • US9692400B2 patent drawing
  • US9692400B2 patent drawing

AI summary

A pulse width widener includes a delay circuit, a processing circuit, and a latch circuit. The delay circuit generates a first signal by delaying an input signal including a first pulse by a delay time. The processing circuit generates a second signal, and the second signal includes information of a second pulse that is temporally extended from the first pulse when a width of the first pulse is smaller than the delay time, based on the first and second signals. The latch circuit stores the second signal and outputs the second pulse as an output signal.